From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa3.mentor.iphmx.com (esa3.mentor.iphmx.com [68.232.137.180]) by sourceware.org (Postfix) with ESMTPS id C0D923858D35 for ; Tue, 10 Oct 2023 15:11:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C0D923858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-CSE-ConnectionGUID: XOcBhTb4QXyx99TPUtB6qg== X-CSE-MsgGUID: A17/+eXoSDuRYZYLBU9hCw== X-IronPort-AV: E=Sophos;i="6.03,213,1694764800"; d="scan'208";a="19058038" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa3.mentor.iphmx.com with ESMTP; 10 Oct 2023 07:11:22 -0800 IronPort-SDR: aJzMpiqKi6prSQm6haCgwsPOwlzCTLIkvcbbABwLUR9H0BWS7c1u3lDojtYRmTAe80YboanOXU 2cKDpXDzvWv2Kc8tAZM0k78vIZ7nlb/WW5g4srjHFqxxdeuz45CYE4O+NFEpfy19sf+xspGMVy IjhXG1Y5B2rLhB4dSinnO8bkTXOLRlAU/FfdnDczbbCqtuIswqaHMWMpGwSobUYUV8FvT71gDt HbiFaL4tm9GiRjsAaoBk/8AhIEi0+I/XvSismnYRak1syxcQVNWQiS2AP7nT1q9zVCvhhBUUgs oUw= Message-ID: <9c350ebd-fd67-4975-abee-68787f97c383@codesourcery.com> Date: Tue, 10 Oct 2023 16:11:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-GB From: Andrew Stubbs Subject: Register allocation cost question To: gcc mailing list Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) To svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, I'm trying to add a new register set to the GCN port, but I've hit a problem I don't understand. There are 256 new registers (each 2048 bit vector register) but the register file has to be divided between all the running hardware threads; if you can use fewer registers you can get more parallelism, which means that it's important that they're allocated in order. The problem is that they're not allocated in order. Somehow the IRA pass is calculating different costs for the registers within the class. It seems to prefer registers a32, a96, a160, and a224. The internal regno are 448, 512, 576, 640. These are not random numbers! They all have zero for the 6 LSB. What could cause this? Did I overrun some magic limit? What target hook might I have miscoded? I'm also seeing wrong-code bugs when I allow more than 32 new registers, but that might be an unrelated problem. Or the allocation is broken? I'm still analyzing this. If it matters, ... the new registers can't be used for general purposes, so I'm trying to set them up as a temporary spill destination. This means they're typically not busy. It feels like it shouldn't be this hard... :( Thanks in advance. Andrew