From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7754 invoked by alias); 11 Jun 2010 22:42:52 -0000 Received: (qmail 7729 invoked by uid 22791); 11 Jun 2010 22:42:50 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM X-Spam-Check-By: sourceware.org Received: from mail-ww0-f47.google.com (HELO mail-ww0-f47.google.com) (74.125.82.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 11 Jun 2010 22:42:40 +0000 Received: by wwb17 with SMTP id 17so1357213wwb.20 for ; Fri, 11 Jun 2010 15:42:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.216.88.20 with SMTP id z20mr5675wee.94.1276296157903; Fri, 11 Jun 2010 15:42:37 -0700 (PDT) Received: by 10.216.229.169 with HTTP; Fri, 11 Jun 2010 15:42:37 -0700 (PDT) In-Reply-To: References: <723761.44710.qm@web33003.mail.mud.yahoo.com> <4C1144F7.1040708@redhat.com> Date: Fri, 11 Jun 2010 23:36:00 -0000 Message-ID: Subject: Re: Scheduling x86 dispatch windows From: Quentin Neill To: "H.J. Lu" Cc: Jeff Law , binutils@sourceware.org, gcc@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2010-06/txt/msg00471.txt.bz2 On Thu, Jun 10, 2010 at 5:23 PM, H.J. Lu wrote: > [snip] > x86 assembler isn't an optimizing assembler. -mtune only does > instruction selection. =A0What you are proposing sounds like an optimizing > assembler to me. Are we going to support scheduling, macro, ...? > -- > H.J. Just to clarify, we are not doing scheduling or macros. The assembler already supported alignment and padding using .align and friends, which can be from the compiler and from hand-written assembly. Now we are seeing more complex alignment rules that are not as simple as it used to be for the older hardware. It will be almost impossible for an assembly programmer to insert the right directives, not to mention any change might invalidate previous alignments. Assembly programmers will be out of luck (that is, unless the compiler becomes the assembler). The essence is we want to insert prefixes (as well as nops) according to certain rules known at encoding time. The mechanism implementing these rules can be abstracted (table driven?) and could be applicable to any hardware having similar features. As gcc does not currently encode and/or generate object code, we are wary of introducing such assembler functionality and want to avoid if possible, instead leveraging the existing binutils infrastructure. --=20 Quentin Neill (with some input from Reza Yazdani)