From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28338 invoked by alias); 27 Dec 2010 15:43:49 -0000 Received: (qmail 28319 invoked by uid 22791); 27 Dec 2010 15:43:47 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL,BAYES_05,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 27 Dec 2010 15:43:42 +0000 Received: by qwg5 with SMTP id 5so8635917qwg.20 for ; Mon, 27 Dec 2010 07:43:41 -0800 (PST) MIME-Version: 1.0 Received: by 10.224.125.13 with SMTP id w13mr11985301qar.93.1293464621137; Mon, 27 Dec 2010 07:43:41 -0800 (PST) Received: by 10.220.12.83 with HTTP; Mon, 27 Dec 2010 07:43:40 -0800 (PST) In-Reply-To: <4D137DDE.8010904@redhat.com> References: <4D137DDE.8010904@redhat.com> Date: Mon, 27 Dec 2010 15:43:00 -0000 Message-ID: Subject: Re: register allocation From: roy rosen To: Vladimir Makarov Cc: gcc@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2010-12/txt/msg00462.txt.bz2 2010/12/23 Vladimir Makarov : > On 12/23/2010 03:13 AM, roy rosen wrote: >> >> Hi All, >> >> I am looking at the code generated by my port and it seems that I have >> a problem that too many copies between registers are generated. >> I looked a bit at the register allocation and wanted to verify that I >> understand its behavior. >> >> Is that true that it first chooses a register class for each pseodo >> and only then starts coloring? >> > Yes, that is true. >> >> I think that my problem is that in my architecture there are two >> register classes which can do all arithmetic operation but class X can >> also do loads and stores and class Y can also do DSP operations. >> >> So when there are for example two DSP operations and between them some >> arithmetic operations I expect to use only class Y but GCC prefers to >> copy registers and do the arithmetic operations using X because for >> some reason it determined that the prefered class for the registers in >> the arithmetic operations is X. >> >> It seems that determining the class does not look at the whole flow >> but rather looks only at insns in which the register appears. >> > Defining classes for pseudos is already one of the most expensive operati= on > in IRA. =A0Looking at the flow would make it even more complicated (I even > don't know how to use this to improve the allocation because it means live > range splitting before coloring and before defining classes which could h= elp > do live range splitting reasonably taking register pressure into account). >> >> Do I understand the situation correctly? > > Yes, I guess. >> >> Is there something I can do about it? > > I'd recommend to try ira-improv branch. =A0I think that part of the probl= em is > in usage of cover classes. =A0The branch removes the cover classes and pe= rmits > IRA to use intersected register classes and that helps to assign better h= ard > registers. > > I tried now this branch and got better results for some cases but still in other cases I get lots of redundent register copies. I might be missing something from the gcc history but I wonder why do we need to limit the coloring stage to select a hard reg from a class that was chosen by a prior stage. Why not simply put in the interference graph edges for all registers which are not possible for a pseudo and let the coloring algorithm select the best hard reg. It seems that choosing a class for a pseudo before the coloring only makes it impossible for the coloring to get to the best solution. Roy.