From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9929 invoked by alias); 22 Mar 2011 06:45:26 -0000 Received: (qmail 9909 invoked by uid 22791); 22 Mar 2011 06:45:25 -0000 X-SWARE-Spam-Status: No, hits=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-gy0-f175.google.com (HELO mail-gy0-f175.google.com) (209.85.160.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 22 Mar 2011 06:45:18 +0000 Received: by gyf1 with SMTP id 1so2839491gyf.20 for ; Mon, 21 Mar 2011 23:45:17 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.4.8 with SMTP id g8mr4726582ybi.335.1300776316659; Mon, 21 Mar 2011 23:45:16 -0700 (PDT) Received: by 10.147.169.16 with HTTP; Mon, 21 Mar 2011 23:45:16 -0700 (PDT) In-Reply-To: References: Date: Tue, 22 Mar 2011 06:45:00 -0000 Message-ID: Subject: Re: Clarification on PowerPC64 Linux ABI From: Rohit Arul Raj To: Andrew Pinski Cc: gcc Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2011-03/txt/msg00319.txt.bz2 Hello Andrew, On Tue, Mar 22, 2011 at 11:41 AM, Andrew Pinski wrote: > On Mon, Mar 21, 2011 at 10:50 PM, Rohit Arul Raj = wrote: >> Hello All, >> >> I have a question regarding PowerPC64 bit ABI. Since GCC generates FP >> instructions for Non FP code, i was running in to issues with >> applications having interrupts (i have seen some threads with people >> complaining about this). > > > What kind of interrupts? My usage is similar to the thread given below: http://old.nabble.com/powerpc-eabi-gcc-no-implicit-FPU-usage-td27185159.html When an interrupt occurs, the FPU is disabled. And while servicing an interrupt, corresponding ISR gets called for which GCC generates code that have FP registers being used even though there is no explicit FPU usage. > Because FP code should only produce an > interrupt at the first usage and that is it. =A0Since all PowerPC64 > machines have a FPU, there will be no emulation needed. =A0The only > other kind of interrupt I can think of is an unaligned load/store for > a FPU load/store. =A0If that happens then you have issues dealing with > unaligned memory which is most like caused by undefined code. =A0Most > PPC64 machines are able to handle word aligned float/double > load/stores without an unaligned exception happening. =A0The reason why > it is undefined because of alignment requirements in the C/C++ > standard. =A0I think you need to do some debugging to figure out why you > get the unaligned exceptions. =A0It is most likely a bug in your code. > > Thanks. > Andrew Pinski > > PS -msoft-float does not work as we don't multilib on -msoft-float for PP= C64. >