From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28316 invoked by alias); 22 Sep 2009 12:31:46 -0000 Received: (qmail 28305 invoked by uid 22791); 22 Sep 2009 12:31:45 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=BAYES_00,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mail-px0-f184.google.com (HELO mail-px0-f184.google.com) (209.85.216.184) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 22 Sep 2009 12:31:40 +0000 Received: by pxi14 with SMTP id 14so3494354pxi.3 for ; Tue, 22 Sep 2009 05:31:38 -0700 (PDT) Received: by 10.114.253.23 with SMTP id a23mr1546251wai.155.1253622698690; Tue, 22 Sep 2009 05:31:38 -0700 (PDT) Received: from Paullaptop (124-170-35-85.dyn.iinet.net.au [124.170.35.85]) by mx.google.com with ESMTPS id 22sm602559pzk.14.2009.09.22.05.31.35 (version=SSLv3 cipher=RC4-MD5); Tue, 22 Sep 2009 05:31:37 -0700 (PDT) Message-ID: From: "Paul Edwards" To: "Ulrich Weigand" Cc: Subject: Re: i370 port Date: Tue, 22 Sep 2009 12:31:00 -0000 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: 7bit Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-09/txt/msg00433.txt.bz2 > I have a theory that if both displacements in the S-type (ie register plus > displacement) address are non-zero, that something fails. So the > next thing I will do is see if I can detect just that situation, and stop > it going into the CLC. I now have that detection in place, and done a self-compile, and all is looking great. No idea if that is producing a technically correct compiler or not though (ie whether my workaround correctly bypasses all circumstances). So that leaves 2 more workarounds which I would like to reverse out. I'll spend some time on them next. BFN. Paul. ; ; cmpmemsi instruction pattern(s). ; (define_expand "cmpmemsi" [(set (match_operand:SI 0 "general_operand" "") (compare (match_operand:BLK 1 "general_operand" "") (match_operand:BLK 2 "general_operand" ""))) (use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 4 "" ""))] "" " { rtx op1, op2; int iv1 = 0; int iv2 = 0; op1 = XEXP (operands[1], 0); if (GET_CODE (op1) == REG || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG && GET_CODE (XEXP (op1, 1)) == CONST_INT && (unsigned) (iv1 = INTVAL (XEXP (op1, 1))) < 4096)) { op1 = operands[1]; } else { op1 = gen_rtx_MEM (BLKmode, copy_to_mode_reg (SImode, op1)); } op2 = XEXP (operands[2], 0); if (GET_CODE (op2) == REG || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG && GET_CODE (XEXP (op2, 1)) == CONST_INT && (unsigned) (iv2 = INTVAL (XEXP (op2, 1))) < 4096)) { op2 = operands[2]; } else { op2 = gen_rtx_MEM (BLKmode, copy_to_mode_reg (SImode, op2)); } /* one circumstance has been found where this short comparison causes an internal error. Could be related to the fact that both displacements were non-zero, which is unusual. So check for that */ if (((iv1 == 0) || (iv2 == 0)) && GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256) { emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, gen_rtx_SET (VOIDmode, operands[0], gen_rtx_COMPARE (SImode, op1, op2)), /* was VOIDmode */ gen_rtx_USE (VOIDmode, operands[3])))); } else { /* implementation suggested by Richard Henderson */ rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); rtx result = operands[0]; rtx mem1 = operands[1]; rtx mem2 = operands[2]; rtx len = operands[3]; if (!CONSTANT_P (len)) len = force_reg (SImode, len); /* Load up the address+length pairs. */ emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0), force_operand (XEXP (mem1, 0), NULL_RTX)); emit_move_insn (gen_rtx_SUBREG (SImode, reg1, GET_MODE_SIZE (SImode)), len); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2)); emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0), force_operand (XEXP (mem2, 0), NULL_RTX)); emit_move_insn (gen_rtx_SUBREG (SImode, reg2, GET_MODE_SIZE (SImode)), len); /* Compare! */ emit_insn (gen_cmpmemsi_1 (result, reg1, reg2)); } DONE; }") ; Compare a block that is less than 256 bytes in length. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (compare:SI (match_operand:BLK 1 "s_operand" "m") (match_operand:BLK 2 "s_operand" "m"))) (use (match_operand:QI 3 "immediate_operand" "I"))] "((unsigned) INTVAL (operands[3]) < 256)" "* { check_label_emit (); mvs_check_page (0, 22, 0); return \"CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; }" [(set_attr "length" "22")] ) ; Compare a block that is larger than 255 bytes in length. ; (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "+d") 0)) ; (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "+d") 0)))) (define_insn "cmpmemsi_1" [(set (match_operand:SI 0 "register_operand" "+d") (compare:SI (mem:BLK (match_operand:DI 1 "register_operand" "+d") ) (mem:BLK (match_operand:DI 2 "register_operand" "+d") ))) (use (match_dup 1)) (use (match_dup 2)) (clobber (match_dup 1)) (clobber (match_dup 2))] "" "* { check_label_emit (); mvs_check_page (0, 18, 0); return \"LA %0,1(0,0)\;CLCL %1,%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; }" [(set_attr "length" "18")] )