From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x933.google.com (mail-ua1-x933.google.com [IPv6:2607:f8b0:4864:20::933]) by sourceware.org (Postfix) with ESMTPS id 574713858001 for ; Fri, 7 Jan 2022 04:25:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 574713858001 Received: by mail-ua1-x933.google.com with SMTP id y4so8230831uad.1 for ; Thu, 06 Jan 2022 20:25:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=b5Po4yzXjRPMp2wWmk2MKYMpnAraiNhkUiYVrNg2ipM=; b=ZMmenhrtfL+k6kWvj2JYRP5Lst1Dfo1U2iOx7yZn4f7UeSRZi816nYhr7BE0LmGj4+ 1veiLUUmmcXP+doZpnwMkSQjSp2M1Zyo1PXs2eedan3BOetZb17Yex8gVmYpD+XMD3Fr 19eJEP1R+nzM5hMK2ulGAGHZgtz6vMH9gQ9OTdm3u+GYbE+PxlYhiV1Mbdn7ATMFUl1U WX/GAPIJ/dpW6OAZIvdE5Q9n1yw8WGF7HenJtAUAJ5P+OSi0ahUPfpvdB/NuTsoOoeMJ MA9M732UkswQ5LwVdK9MGpIakLGYlqNOD3fcp+9W9iWOSTfPzKuj+wyYY0oVjuNNzLXe jg9w== X-Gm-Message-State: AOAM532nYTVctYqyLbFwJPh4f+AqZoAAW2rZ5j9hPpGsOE0gvcAMgoB9 f0luhG5PH/B5LQwg1d025d4ksf85VeA+ApCJdUCyVGAnrEY= X-Google-Smtp-Source: ABdhPJzLqSiPG3wdJKLed0NhP2DFoK6vwKboxUpnrCCcXphzKtJNPC4ZivVmcJg0eksFaT0o/nIvjnUOjQvKyzo8/Dw= X-Received: by 2002:a05:6102:31b3:: with SMTP id d19mr19981448vsh.79.1641529547833; Thu, 06 Jan 2022 20:25:47 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Andrew Pinski Date: Thu, 6 Jan 2022 20:25:35 -0800 Message-ID: Subject: Re: Why doesn't this pattern match? To: Andras Tantos Cc: GCC Development Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 07 Jan 2022 04:25:50 -0000 On Thu, Jan 6, 2022 at 8:13 PM Andras Tantos wrot= e: > > Hello! > > My name is Andras Tantos and I just joined this list, so if I'm asking > something off-topic or not following the rules of the community, please > let me know. > > What I'm working on is to port GCC (and Binutils) to a new CPU ISA, I > call 'brew'. During developing for this target, I got the following > error: How are the following constraints defined: W,A,B Does one include the pc register? Otherwise you have a mismatch between the predicate brew_general_mov_src_operand (which accepts the pc register) and the constraint which does not. Thanks, Andrew Pinski > > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > first.c: In function =E2=80=98test_call=E2=80=99: > first.c:61:52: error: insn does not satisfy its constraints: > 61 | int test_call(int a, int b) { return test_qm(a,b); } > | ^ > (insn 25 8 9 (set (reg:SI 6 $r6) > (reg:SI 0 $pc)) "first.c":61:38 17 {*movsi} > (nil)) > during RTL pass: final > first.c:61:52: internal compiler error: in final_scan_insn_1, at > final.c:2811 > 0x6c4c23 _fatal_insn(char const*, rtx_def const*, char const*, int, > char const*) > ../../brew-gcc/gcc/rtl-error.c:108 > 0x6c4c4f _fatal_insn_not_found(rtx_def const*, char const*, int, char > const*) > ../../brew-gcc/gcc/rtl-error.c:118 > 0x643585 final_scan_insn_1 > ../../brew-gcc/gcc/final.c:2811 > 0xb1ef3f final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*) > ../../brew-gcc/gcc/final.c:2940 > 0xb1f207 final_1 > ../../brew-gcc/gcc/final.c:1997 > 0xb1fbe6 rest_of_handle_final > ../../brew-gcc/gcc/final.c:4285 > 0xb1fbe6 execute > ../../brew-gcc/gcc/final.c:4363 > Please submit a full bug report, > with preprocessed source if appropriate. > Please include the complete backtrace with any bug report. > See for instructions. > <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< > > Clearly, the compiler couldn't find a rule that works for this register > move. The relevant section of the .md file is: > > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > (define_expand "movsi" > [(set (match_operand:SI 0 "general_operand" "") > (match_operand:SI 1 "general_operand" ""))] > "" > " > { > /* If this is a store, force the value into a register. */ > if (! (reload_in_progress || reload_completed)) > { > if (MEM_P (operands[0])) > { > operands[1] =3D force_reg (SImode, operands[1]); > if (MEM_P (XEXP (operands[0], 0))) > operands[0] =3D gen_rtx_MEM (SImode, force_reg (SImode, XEXP > (operands[0], 0))); > } > else > if (MEM_P (operands[1]) > && MEM_P (XEXP (operands[1], 0))) > operands[1] =3D gen_rtx_MEM (SImode, force_reg (SImode, XEXP > (operands[1], 0))); > } > }") > > (define_insn "*movsi" > [(set (match_operand:SI 0 > "nonimmediate_operand" "=3Dr,r,r,W,A,B,r,r,r") > (match_operand:SI 1 "brew_general_mov_src_operand" > "O,r,i,r,r,r,W,A,B"))] > "register_operand (operands[0], SImode) > || register_operand (operands[1], SImode)" > "@ > %0 <- %0 - %0 > %0 <- %1 > %0 <- %1 > mem[%0] <- %1 > mem[%0] <- %1 > mem[%0] <- %1 > %0 <- mem[%1] > %0 <- mem[%1] > %0 <- mem[%1]" > ) > <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< > > As you can imagine, I'm fairly new to GCC development, so I must be > making some rookie mistake here, but I would have thought that the > second alternative in the "*movsi" rule above would match the pattern. > > brew_general_mov_src_operand is defined as follows: > > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > (define_predicate "brew_general_mov_src_operand" > (match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const") > { > /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */ > if (MEM_P (op) && GET_CODE (XEXP (op, 0)) =3D=3D LABEL_REF) > return 1; > > if (MEM_P (op) > && GET_CODE (XEXP (op, 0)) =3D=3D PLUS > && GET_CODE (XEXP (XEXP (op, 0), 0)) =3D=3D REG > && GET_CODE (XEXP (XEXP (op, 0), 1)) =3D=3D CONST_INT > ) > return 1; > /* Any register is good too */ > if (REG_P(op)) > return 1; > /* PC as source is also acceptable */ > if (op =3D=3D pc_rtx) > return 1; > return general_operand (op, mode); > }) > <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< > > Thanks for all the help, > Andras > >