From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7954 invoked by alias); 18 Feb 2014 14:05:05 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 7943 invoked by uid 89); 18 Feb 2014 14:05:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-vc0-f194.google.com Received: from mail-vc0-f194.google.com (HELO mail-vc0-f194.google.com) (209.85.220.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 18 Feb 2014 14:04:35 +0000 Received: by mail-vc0-f194.google.com with SMTP id hu8so3677195vcb.1 for ; Tue, 18 Feb 2014 06:04:32 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.221.2.138 with SMTP id nu10mr338459vcb.52.1392732272685; Tue, 18 Feb 2014 06:04:32 -0800 (PST) Received: by 10.59.9.2 with HTTP; Tue, 18 Feb 2014 06:04:32 -0800 (PST) Date: Tue, 18 Feb 2014 14:05:00 -0000 Message-ID: Subject: [LM-32] Code generation for address loading From: FX MOREL To: gcc@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2014-02/txt/msg00301.txt.bz2 Hi everyone, I am developing on a custom design using the LatticeMico32 architecture and I use gcc 4.5.1 to compile C code for this arch. In this architecture, the loading of an address 0xHHHHLLLL always takes two assembly instructions to fetch the address because immediates are on 16 bits : mvhi r1, 0xHHHH ori r1, r1, 0xLLLL ... lw r2, r1 In my situation, nearly all the symbols are located in the same 64kB region and their address share the same hi-part, so I am trying to minimize the overload of always using two instructions when only one is needed. In the C code, regrouping variables in structure will generate code where memory is accessed through an offset of the base address of the structure which is only loaded once per function, hence a gain in code size. But the extent of this technique is still limited by C code readability constraints and there is still at least one penalty in each function to load the first address. I was imagining something with a fixed register (say r23, declared as -ffixed in compilation flags) that would be loaded with the addresses' hi-part at reset (in the same ways that r0 is set to 0) and then each address loading phase would only consist in one instruction : ori r1, r23, 0xLLLL I have tried to play around with machine description file of the lm32 architecture to achieve my goal but I need some kind of constraints or condition to check where is my symbol before using this shortened version of address loading (Even if nearly all of the symbols are located within the same 64kB, some are still located in other memory regions and I don't want to touch them !) Because the symbol mapping phase is done during linking, I have little chance to know the future symbol address at code generation but is there some way I could make this work ? If I affect the symbol to a dedicated section (with the __attribute__ ((section())) directive ), is there a way to know its section during code generation ? I understand that I am asking for a very 'dangerous' advice but again, this will only be a custom optimization for a custom design. Thank you. F-X Morel