From: sravan megan <sravan22021987@gmail.com>
To: gcc@gcc.gnu.org
Subject: load reverse
Date: Thu, 08 Aug 2013 11:59:00 -0000 [thread overview]
Message-ID: <CAESop7XA5rDDgPi-CR+r4aTgXQJ_CSKPp7_vSW75LUXhyGW+Tw@mail.gmail.com> (raw)
Hi All,
I am new to GCC. I was working in an Embedded processor with
GCC-4.6.4 version.
I need to add load/store reverse instructions to the MD file.
My instructions will look as below:
LWX Rd,Ra,Rb
operation: Addr := Ra + Rb
Rd := *Addr (loading data with the opposite endianness)
SWX Rd,Ra,Rb
operation: Addr := Ra + Rb
*Addr := Rd (storing data with the opposite endianness)
To add the above instructions in to md file I tried below pattern in md file
(define_insn "movsi_rev"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
(bswap: SI (match_operand:SI 1 "move_src_operand" "m,d")))]
""
"@
lwx\t%0,%1,%0
swx\t%0,%1,%0"
[(set_attr "type" "load,store")
(set_attr "mode" "SI")
(set_attr "length" "4,4")])
I wrote a small testcase which is generating swx instruction but
the operands are more due to which it is failing in assembler phase
ex:
int store_rev(int *n)
{
return ((((*n) & 0xff000000) >> 24)
| (((*n) & 0x00ff0000) >> 8)
| (((*n) & 0x0000ff00) << 8)
| (((*n) & 0x000000ff) << 24));
}
for the above store_rev function I need to generate only single swx instruction.
I was successful in generating the swx instruction but instead of 3
registers compiler is generating one extra operand "0" swx r0,r2,0,r0
ex: instead of swx r0,r2,r0 it is generating swx r0,r2,0,r0
can anyone please help me in removing the extra operand in the above
instruction.
Thanks,
Sravan
next reply other threads:[~2013-08-08 11:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-08 11:59 sravan megan [this message]
2013-08-12 4:22 ` sravan megan
2013-08-12 8:28 ` Andrew Haley
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