From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28704 invoked by alias); 20 Mar 2012 10:35:02 -0000 Received: (qmail 28615 invoked by uid 22791); 20 Mar 2012 10:35:00 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-pz0-f47.google.com (HELO mail-pz0-f47.google.com) (209.85.210.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 20 Mar 2012 10:34:37 +0000 Received: by dado14 with SMTP id o14so10908820dad.20 for ; Tue, 20 Mar 2012 03:34:37 -0700 (PDT) Received: by 10.68.194.3 with SMTP id hs3mr48240842pbc.119.1332239677228; Tue, 20 Mar 2012 03:34:37 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.193.2 with HTTP; Tue, 20 Mar 2012 03:33:24 -0700 (PDT) In-Reply-To: References: From: Mohamed Shafi Date: Tue, 20 Mar 2012 10:35:00 -0000 Message-ID: Subject: Re: Reloading going wrong. Bug in GCC? To: GCC Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2012-03/txt/msg00306.txt.bz2 ping !!!. Any help on http://gcc.gnu.org/ml/gcc/2011-09/msg00150.html shafi On 14 September 2011 15:07, Mohamed Shafi wrote: > Hi, > > I am working on a 32bit private target which has the following restriction > > 1. store/load can happen only through a general purpose register (GP_REGS) > 2. base register should be an address register (AD_REGS) > 3. moves between GP_REGS and AD_REGS can happen only through PT_REGS > > In a PRE_MODIFY instruction when both the base register and the output > register gets spilled the reloading is going wrong. > > befor IRA pass > ~~~~~~~~~~~ > (insn 259 336 317 2 ../rld_bug.c:94 (set (reg:QI 234 [+1 ]) > =A0 =A0 =A0 =A0(mem/s/j/c:QI (pre_modify:PQI (reg/f:PQI 233) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(plus:PQI (reg/f:PQI 233) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int 1 [0x1]))) [0+1 S1 A32]= )) 7 {movqi_op} > (expr_list:REG_INC (reg/f:PQI 233) > =A0 =A0 =A0 =A0(nil))) > > after IRA pass > ~~~~~~~~~~~ > Reloads for insn # 259 > Reload 0: GP_REGS, RELOAD_FOR_OPADDR_ADDR (opnum =3D 1), can't combine, > secondary_reload_p > =A0 =A0 =A0 =A0reload_reg_rtx: (reg:PQI 11 g11) > Reload 1: PT_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 1), can't > combine, secondary_reload_p > =A0 =A0 =A0 =A0reload_reg_rtx: (reg:PQI 12 as0) > =A0 =A0 =A0 =A0secondary_in_reload =3D 0 > Reload 2: GP_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 1), can't > combine, secondary_reload_p > =A0 =A0 =A0 =A0reload_reg_rtx: (reg:PQI 11 g11) > Reload 3: PT_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 1), can't > combine, secondary_reload_p > =A0 =A0 =A0 =A0reload_reg_rtx: (reg:PQI 13 as1) > =A0 =A0 =A0 =A0secondary_out_reload =3D 2 > > Reload 4: reload_in (PQI) =3D (reg/f:PQI 233) > =A0 =A0 =A0 =A0reload_out (PQI) =3D (reg/f:PQI 233) > =A0 =A0 =A0 =A0AD_REGS, RELOAD_OTHER (opnum =3D 1) > =A0 =A0 =A0 =A0reload_in_reg: (reg/f:PQI 233) > =A0 =A0 =A0 =A0reload_out_reg: (reg/f:PQI 233) > =A0 =A0 =A0 =A0reload_reg_rtx: (reg:PQI 31 a3) > =A0 =A0 =A0 =A0secondary_in_reload =3D 1, secondary_out_reload =3D 3 > > Reload 5: reload_out (QI) =3D (reg:QI 234 [+1 ]) > =A0 =A0 =A0 =A0GP_REGS, RELOAD_FOR_OUTPUT (opnum =3D 0) > =A0 =A0 =A0 =A0reload_out_reg: (reg:QI 234 [+1 ]) > =A0 =A0 =A0 =A0reload_reg_rtx: (reg:QI 11 g11) > > > (insn 744 336 745 2 ../rld_bug.c:94 (set (reg:PQI 11 g11) > =A0 =A0 =A0 =A0(mem/c:PQI (plus:PQI (reg/f:PQI 32 sp) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int -24 [0xffffffffffffffe8])) [99 = %sfp+8 S1 > A32])) 9 {movpqi_op} (nil)) > > (insn 745 744 746 2 ../rld_bug.c:94 (set (reg:PQI 12 as0) > =A0 =A0 =A0 =A0(reg:PQI 11 g11)) 9 {movpqi_op} (nil)) > > (insn 746 745 259 2 ../rld_bug.c:94 (set (reg:PQI 31 a3) > =A0 =A0 =A0 =A0(reg:PQI 12 as0)) 9 {movpqi_op} (nil)) > > (insn 259 746 747 2 ../rld_bug.c:94 (set (reg:QI 11 g11) > =A0 =A0 =A0 =A0(mem/s/j/c:QI (pre_modify:PQI (reg:PQI 31 a3) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(plus:PQI (reg:PQI 31 a3) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int 1 [0x1]))) [0+1 S1 A32]= )) 7 {movqi_op} > (expr_list:REG_INC (reg:PQI 31 a3) > =A0 =A0 =A0 =A0(nil))) > > (insn 747 259 748 2 ../rld_bug.c:94 (set (reg:PQI 13 as1) > =A0 =A0 =A0 =A0(reg:PQI 31 a3)) 9 {movpqi_op} (nil)) > > (insn 748 747 749 2 ../rld_bug.c:94 (set (reg:PQI 11 g11) > =A0 =A0 =A0 =A0(reg:PQI 13 as1)) 9 {movpqi_op} (nil)) > > (insn 749 748 750 2 ../rld_bug.c:94 (set (mem/c:PQI (plus:PQI (reg/f:PQI = 32 sp) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int -24 [0xffffffffffffffe8])) [99 = %sfp+8 S1 A32]) > =A0 =A0 =A0 =A0(reg:PQI 11 g11)) 9 {movpqi_op} (nil)) > > (insn 750 749 751 2 ../rld_bug.c:94 (set (mem/c:QI (plus:PQI (reg/f:PQI 3= 2 sp) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int -29 [0xffffffffffffffe3])) [99 = %sfp+3 S1 A32]) > =A0 =A0 =A0 =A0(reg:QI 11 g11)) 7 {movqi_op} (nil)) > > > After IRA pass for insn 259 1st the modified address is stored into > its spilled location and then the modified value is stored. As you can > see from the instructions same register (g11) is used for Reload 5 and > 2, and hence the modified value is getting corrupted and hence the > modified address gets stored instead of modified value (insn 749 and > insn 750). I am not able to figure out where this is going wrong in > the reload phase. I suspect that this is a GCC issue. > > Can some one give me some pointers to resolve this issue? > > Regards, > Shafi