From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 60121 invoked by alias); 6 May 2019 18:12:35 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 60112 invoked by uid 89); 6 May 2019 18:12:34 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: =?ISO-8859-1?Q?No, score=0.5 required=5.0 tests=AWL,BAYES_00,BODY_8BITS,GARBLED_BODY,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=no version=3.3.1 spammy=HX-Languages-Length:1602, *min_, spike, =d0=b5=d0=b9?= X-HELO: mail-vs1-f44.google.com Received: from mail-vs1-f44.google.com (HELO mail-vs1-f44.google.com) (209.85.217.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 06 May 2019 18:12:33 +0000 Received: by mail-vs1-f44.google.com with SMTP id s4so4547796vsl.2 for ; Mon, 06 May 2019 11:12:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=QIIbGE9xMjDLFyjDoxEZ4OdEH6jb0hDwS0iSaaiijn4=; b=H/iHOEgHzpjCmUx/vV5KPe4h2sCsEPraxeSFmoBSugTt1BvYcXTDb/QCXa2EEcUUYR 5GEE4mbByUGK60A2n2Tiz8xIJbxVGKjIyrEukZSyB7eOpeei3inP93R1oILkHsnOa2Mv lxltDPBmT+1T2hFnhHDwTTWeJY1QZed/E31KbG9Bw7yn+G42u6eJlEs9DjyjT7fQJ1m6 rK25aPkT26Mo+D/Y8nKzJqOhYd48N6TdlGxrT1LzbM5XcNsaQE5qE/SpA2PHkifhX3oF /cZwp5U6g1Ha8oLPctNPQYsUx7S4/eFKqYVQT8KfkkE+/nZXCKKiXgyrDlwnKNIFF8Wk mprw== MIME-Version: 1.0 References: <1557147718.189664150@f513.i.mail.ru> In-Reply-To: <1557147718.189664150@f513.i.mail.ru> From: Jim Wilson Date: Mon, 06 May 2019 18:12:00 -0000 Message-ID: Subject: Re: Please help!!! To: =?UTF-8?B?0JDQu9C10LrRgdC10Lkg0KXQuNC70LDQtdCy?= Cc: GCC Development Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00047.txt.bz2 On Mon, May 6, 2019 at 6:02 AM =D0=90=D0=BB=D0=B5=D0=BA=D1=81=D0=B5=D0=B9 = =D0=A5=D0=B8=D0=BB=D0=B0=D0=B5=D0=B2 via gcc wrote: > Gcc riscv won`t emit my insns, binutils and spike(riscv sim) work correct= ly, but gcc don`t. I want to add min/max for integer, gcc compiling correct= , sim executing correctly. > (define_insn "*min_" > [(set (match_operand:GPR 0 "register_operand" "=3Dr") > (smin:GPR (match_operand:X 1 "register_operand" " r") > (match_operand:X 2 "register_operand" " r")))] > "" > "min\t%0,%1,%2" > [(set_attr "type" "move") > (set_attr "mode" "")]) You must have patterns named sminXi3 where X can be s and/or d. Likewise for smaxXi3. Once the named patterns exist, then gcc will automatically call the named patterns to generate RTL when appropriate. Then later passes like combine can create new RTL from the min/max pattern RTL. See for instance how the existing FP min/max patterns work. The pattern name is important. You might also consider adding uminXi3 and umaxXi3 patterns. You can find a list of supported named patterns in the gcc docs. Also note that the RTL that you generate must look sensible. You have a smin:GPR operation that is accepting Xmode operands which is not OK. The modes must match. You can use sign_extend/zero_extend to sign/zero extend a smaller mode to a larger mode, and subreg to reduce a larger mode to a smaller one. These will have to be separate patterns. But once you have the basic smin/smax patterns, combine can create the sign_extend/whatever versions for you. See for instance how the addsi3 and addsi3_extend* patterns work. Jim