From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id EC6683858CDB for ; Fri, 26 May 2023 12:31:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC6683858CDB Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2Waz-0002HX-FM for gcc@gnu.org; Fri, 26 May 2023 08:31:03 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-96f7377c86aso111576266b.1 for ; Fri, 26 May 2023 05:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685104259; x=1687696259; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HNWGY13kA59ljBeiOuvumrbWCR+8OPGb2Zw+n9vj1SY=; b=GhG35aq4HGsFGrpKEO8+YlxxwY98MNbTIxSV6/BMyFUyj2W3hALEf7WgTsNetXf6Gx z82J2HYhHKEzsPonBunk06+SkN/yr3xgSc6Vf7NT087Yh/JfbmqSjsViMhrjT7rnLDTn GFobfG/7+LmdqgkPaXJ//oQOcLX9SqB1mns8eCCZwYz13F9/Eh1Z8dZSJnuoN/5YRmpK MmVIsxw3QqHqY0LwXTtzlQ6V5vTUfR/7s8nVGEVK+Xk8GWu+fRjq4Inuqa/Z5g2br24q seIKgH8Pf9gdKxGZglVnTWbf0xJRiV6QycBDqRyvKeIkpf4YN4Bl+lAd5rb/tHl6W4pf eRDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685104259; x=1687696259; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HNWGY13kA59ljBeiOuvumrbWCR+8OPGb2Zw+n9vj1SY=; b=IKzLPppPhVu1iwgmWJr+/E7monqdcUjgx++3fVlHHrvNhhp90HOpYpkGx4SRaEjcQU QzLXgGnhrZW/y/HkKuDoBQvshWIJGfeU96pbNM2C0SmUWaQmPK/fFKrDKHMoJIwnEtU/ wSGRYFaihC9KAgWORjXvKbQdNUFOUmczQn9k1EQNa06aYk+rP4b4vaAYVhZLL6utkqMz zTzu86KL5wfQ+HAleykG7mqlrTQQ19kUMjS0QRjz3ap0lrpEykpQJ8FLsJVmUxgJODd6 X03CVp54CKkDAni+rpEDKFx8blbbcAPSBtskM2xI/YPUy0CcKY/2WKiJszzL3uD1LnoI /Dlg== X-Gm-Message-State: AC+VfDxnAKamDDWMxx3FRJ45JBe7dyCTQJJVQDSLoh/QR0IYaG+WxtZC vRy4tIYSK97qDK0UfC/zpcRhrvHOV+OgA1EgZKM= X-Google-Smtp-Source: ACHHUZ69NEvT4gLq05Yv7j3w28I2oR0h3oGPtkvf6yl8XQPPeUr50np/e5eQR7zaRweSCcHb69UMy76lalOIX5PO2V8= X-Received: by 2002:a17:907:6e8a:b0:969:e7da:fcb1 with SMTP id sh10-20020a1709076e8a00b00969e7dafcb1mr2345411ejc.13.1685104259158; Fri, 26 May 2023 05:30:59 -0700 (PDT) MIME-Version: 1.0 References: <51071A92918346ABBC6B5703179F5174@H270> <896EB515110646CEBAA84E98E273E4B8@H270> <4BD5D8BA8E0F45098CC3E2B188A216E6@H270> In-Reply-To: From: Jonathan Wakely Date: Fri, 26 May 2023 13:30:48 +0100 Message-ID: Subject: Re: Will GCC eventually support SSE2 or SSE4.1? To: Stefan Kanthak Cc: Jakub Jelinek , gcc@gnu.org, Andrew Pinski Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=jwakely.gcc@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,DKIM_VALID_EF=-0.1,FREEMAIL_FROM=0.001,RCVD_IN_DNSWL_NONE=-0.0001,SPF_HELO_NONE=0.001,SPF_PASS=-0.001,T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_PASS,SPF_SOFTFAIL,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 26 May 2023 at 13:23, Stefan Kanthak wrote: > > "Jonathan Wakely" wrote: > > > On Fri, 26 May 2023 at 12:42, Stefan Kanthak wrote: > >> Why does the documentation FAIL to specify that CPU features given by > >> -m* override -m32 or enables them in ADDITION to those enabled by -march=? > > > > Because it's obvious. If you ask for sse2 you get it. > > ARGH! The documentation for -m32 contradicts > > | -m32 > ... > | The -m32 option sets int, long, and pointer types to 32 bits, and > | generates code that runs on any i386 system. > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > I find it very SURPRISING that you're only just learning the basics of > > how to use gcc NOW, after YELLING about all the OUCH. > > I'm NOT surprised that you don't grok it! > > gcc -msse4.1 -m32 -march=core2 ... > > Which -m* options win here? > Do -m32 or -march=core2 override -msse4.1? No, because -m32 says to generate code for the 32-bit model, it doesn't select an instruction set. A multilib x86_64 compiler has a default 64-bit arch and a default 32-bit arch. If you don't configure GCC with --with-arch-32 and/or --with-arch-64 then you get -march=x86-64 for both 32-bit and 64-bit. Using -m32 without -march will use the default 32-bit arch, which is probably x86-64. Using -m32 with any explicit -march will override the default, and use the one you specified. And I already said that -march selects the base instruction set, and then -msse4.1 adds to that, enabling sse4.1 as well. I said: -march enables the instructions listed for the relevant cpu family, then using -mxxx or -mno-xxx adds or removes particular instruction sets from the ones enabled by -march. So -march=core2 selects the instruction sets listed in the docs, and then -msse4.1 adds to that. I don't know how to say it more clearly. All this could have been explained easily and without conflict if you'd use the right mailing list in the first place and asked how things work, instead of storming in acting like a clown and being rude. "Will GCC eventually support SSE2 or SSE4.1?" is confrontational, and makes you look dumb. And it's just got worse since then.