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From: Jonathan Wakely <jwakely.gcc@gmail.com>
Date: Thu, 13 Oct 2022 21:15:04 +0100
Message-ID: <CAH6eHdSnx-V0SmS969pe=H=HfpcVFOnS-gPhJ1xcDyeXd509mQ@mail.gmail.com>
Subject: Re: Fences/Barriers when mixing C++ atomics and non-atomics
To: Vineet Gupta <vineetg@rivosinc.com>
Cc: tech-unprivileged@lists.riscv.org, gcc@gcc.gnu.org, 
	Uros Bizjak <ubizjak@gmail.com>, Hans Boehm <hboehm@google.com>, 
	Hongyu Wang <hongyu.wang@intel.com>
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On Thu, 13 Oct 2022 at 20:31, Vineet Gupta wrote:
>
> Hi,
>
> I have a testcase (from real workloads) involving C++ atomics and trying
> to understand the codegen (gcc 12) for RVWMO and x86.
> It does mix atomics with non-atomics so not obvious what the behavior is
> intended to be hence some explicit CC of subject matter experts
> (apologies for that in advance).
>
> Test has a non-atomic store

And a non-atomic load of 'g'

> followed by an atomic_load(SEQ_CST). I
> assume that unadorned direct access defaults to safest/conservative seq_cst.

Yes, the two functions below are identical.

>
>     extern int g;
>     std::atomic<int> a;
>
>     int bar_noaccessor(int n, int *n2)
>     {
>          *n2 = g;
>          return n + a;
>     }
>
>     int bar_seqcst(int n, int *n2)
>     {
>          *n2 = g;
>          return n + a.load(std::memory_order_seq_cst);
>     }
>