From: Shiva Chen <shiva0217@gmail.com>
To: Renlin Li <renlin.li@arm.com>, yufeng.zhang.uk@googlemail.com
Cc: "gcc@gcc.gnu.org" <gcc@gcc.gnu.org>
Subject: Re: Aarch64 implementation for dwarf exception handling
Date: Thu, 13 Feb 2014 15:37:00 -0000 [thread overview]
Message-ID: <CAH=PD7bZra7W6GyySYzHfR8zAgtuXFmbGP6wRczHxXqeCVdaKA@mail.gmail.com> (raw)
In-Reply-To: <52FCD786.1040407@arm.com>
Hi, Yufeng
Sorry, I don't have any testcase
I just mis-understanding the implementation.
Hi, Renlin
Thanks to point out my mis-understanding.
I didn't aware that LP would in different position between FP needed
(bottom of callee) and FP not needed(top of callee).
I have check the aarch64_layout_frame() and find out the FP/LP will
push as last register by aarch64_save_or_restore_callee_save_registers
() if FP is not needed.
Thanks for your kindly help,
I really appreciate it.
Shiva
2014-02-13 22:32 GMT+08:00 Renlin Li <renlin.li@arm.com>:
> On 13/02/14 02:14, Shiva Chen wrote:
>>
>> Hi,
>>
>> I have a question about the implementation of
>>
>> aarch64_final_eh_return_addr
>>
>> which is used to point out the return address of the frame
>>
>> According the source code
>>
>> If FP is not needed
>>
>> return gen_frame_mem (DImode,
>> plus_constant (Pmode,
>> stack_pointer_rtx,
>> fp_offset
>> +
>> cfun->machine->frame.saved_regs_size
>> - 2 * UNITS_PER_WORD));
>>
>>
>> According the frame layout
>>
>> +-------------------------------+ <-- arg_pointer_rtx
>> |
>> | callee-allocated save area
>> | for register varargs
>> |
>> +-------------------------------+
>> |
>> | local variables
>> |
>> +-------------------------------+ <-- frame_pointer_rtx
>> |
>> | callee-saved registers
>> |
>> +-------------------------------+
>> | LR'
>> +-------------------------------+
>> | FP'
>> P+-------------------------------+ <-- hard_frame_pointer_rtx
>> | dynamic allocation
>> +-------------------------------+
>> |
>> | outgoing stack arguments
>> |
>> +-------------------------------+ <-- stack_pointer_rtx
>>
>> Shouldn't the return value be
>>
>> return gen_frame_mem (DImode,
>> plus_constant (Pmode,
>> stack_pointer_rtx,
>> fp_offset
>> + 2* UNITS_PER_WORD));
>>
>> Or I just mis-understanding something ?
>>
>>
>> Hope someone could give me a tip.
>>
>> It would be very helpful.
>>
>> Thanks
>>
>> Shiva Chen
>>
> Hi,
>
> If frame pointer is not needed. The prologue routine will store the callee
> saved registers to stack according to ascending order, which means X0 will
> be saved first if needed, and X30(LR) will be the last if it's pushed into
> stack.
>
> Please check the source code, aarch64_layout_frame().
>
> As the comment above the code also indicates, LR would be at the top of the
> saved registers block().
>
> By the way, there is one additional stack slot might be needed to keep stack
> pointer 16-byte aligned, so - 2 * UNITS_PER_WORD is needed to adjust the
> load address.
>
> +-------------------------------+ <-- arg_pointer_rtx
> |
> +-------------------------------+ <-- frame_pointer_rtx
> | dummy
> | LR
> | bla...bla...
> | x3
> | x2
> | x1
> | x0
> P +-------------------------------+ <-- hard_frame_pointer_rtx
> |
> +-------------------------------+ <-- stack_pointer_rtx
>
>
> Kind regards,
> Renlin
>
prev parent reply other threads:[~2014-02-13 15:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-13 2:15 Shiva Chen
2014-02-13 11:41 ` Yufeng Zhang 张玉峰
2014-02-13 14:32 ` Renlin Li
2014-02-13 15:37 ` Shiva Chen [this message]
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