From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from fencepost.gnu.org (fencepost.gnu.org [IPv6:2001:470:142:3::e]) by sourceware.org (Postfix) with ESMTPS id 79E693846033 for ; Mon, 12 Apr 2021 00:08:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 79E693846033 Received: from eggs.gnu.org ([2001:470:142:3::10]:36084) by fencepost.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.82) (envelope-from ) id 1lVk7m-0006iX-Jt for gcc@gnu.org; Sun, 11 Apr 2021 20:08:18 -0400 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]:33649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lVk7k-00069l-Lj for gcc@gnu.org; Sun, 11 Apr 2021 20:08:18 -0400 Received: by mail-lj1-x231.google.com with SMTP id p23so9528865ljn.0 for ; Sun, 11 Apr 2021 17:08:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Yi+VEme3TUepg/OpF9YAlQJDq6Dz3KbdyrXtaVb0oUs=; b=P5LaA/twK5dKBKyWhWFDU5iu5AUhE6A+tUhVkcvAhTe1vxgh67/38uOPvT5r47ilZg xf4izvTmSgqJqSOe1z1KycUBeDG5/Zbz9mhnABE1xYrrnF71YiXtiy/rVqMBROJ5/MM3 LcggZKe0efw/4m79coyE7GJuQyx5Rxrf2kCKCe+xxzbhGaQvzHTiSGaIRF+eHpC6Kvt9 dsZWaXl4ryafXyoczO7xcgvBSwt4kxxm8UFOaliTEWfRdhLhT63EG71IGSu2YLp11sp7 2WIpcnFMcWfkcpT/v3d0kamPYQvugKU2FkAbXlrsa/shdneCb1Vjv4Hq6EXD6pPAtk88 OGHg== X-Gm-Message-State: AOAM533NLdgXJyGqBPoSF6lvVU9o+7lbOGDsMukIjkSAvm7G6W58e4dQ moBudherNTIicAWQBVdCGe0fe0NVd1SsSAhnVP51tA== X-Google-Smtp-Source: ABdhPJwSBEANVl+vdlElR8Smp/dXJUNnvKyxt3gIbOOeDT7nkv7vH8RWdVSFh1lp3frMOIs87mm0xaAlE8GfIdAQeYM= X-Received: by 2002:a2e:819a:: with SMTP id e26mr16249101ljg.222.1618186093775; Sun, 11 Apr 2021 17:08:13 -0700 (PDT) MIME-Version: 1.0 References: <06eb8287-e6bb-270f-e5a5-730c10bb31ef@hesbynett.no> <5a4a24bf9e3cc2299793c53516f6a20c@appliantology.com> <20210410201052.841C433CAC@vlsi1.gnat.com> <1e307343-c6cd-fcc8-d734-623b70619081@pfeifer.com> <20210411133048.A819833CAC@vlsi1.gnat.com> <20210411142529.GA30643@jocasta.intra> <20210411143704.A79A733CAC@vlsi1.gnat.com> In-Reply-To: From: Ian Lance Taylor Date: Sun, 11 Apr 2021 17:08:02 -0700 Message-ID: Subject: Re: GCC association with the FSF To: David Brown Cc: Richard Kenner , John Darrington , gcc@gnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=iant@google.com; helo=mail-lj1-x231.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_PASS, TXREP, USER_IN_DEF_DKIM_WL autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Apr 2021 00:08:21 -0000 On Sun, Apr 11, 2021 at 8:04 AM David Brown wrote: > > On 11/04/2021 16:37, Richard Kenner via Gcc wrote: > >> I guess my point is that the direction in which a project *does* go is not > >> always the direction in which it *should* go. > > > > I agree. And depending on people's "political" views, that can either be > > an advantage or disadvantage of the free software development model. > > > >> To give just one small practical example, I'm told (by people who are more > >> familiar with GCC internals than I) that it is not feasible with today's > >> GCC to port to backends which have a small number of registers. > > > > [Finally, a technical discussion in this thread!] > > > > It never really has been. Maybe it's not even possible now (I don't > > know), but if you tried it in the past the results would never have > > been very good. Almost all multi-backend systems operate by having > > very large numbers of expressions at all levels, which you gradually > > lower to actual registers. This works quite well if you have enough > > registers to hold the high-usage expressions in them, but when you > > have high register pressure, the model breaks down completely. > > Although the situation may well have gotten worse in recent versions > > that I'm not familiar with, I'd say that GCC was probably doing a > > *better* job with a small number of registers in more recent versions > > than in older ones: "reload" was particularly bad when there was high > > register pressure. > > > > When your main constraint is register pressure, in order to get > > high-quality results, I think you almost have to change the entire > > philosophy of compilation, to the point I think where you have an > > almost entirely different compilation chain for such machines. > > > > Low register count cpu designs have been out of fashion for quite some > time now (perhaps precisely because they are not a good fit for common > compiler strategies). They are mostly found in older families, such as > the 8-bit CISC designs in older microcontrollers (8051, PIC, COP8, 6502, > etc.). And you are absolutely right that you need a different way of > thinking in order to get the best out of such chips - low register count > is only one aspect. Other issues are few or no flexible pointer > registers, no "SP + offset" addressing modes for efficient parameters or > stack frames, banked ram and code blocks, and multiple separate address > spaces. Good toolchains for such devices need to work in a very > different way, and typically encompass compilation, assembling and > linking in one "omniscient" build so that variables, parameters, etc., > can be placed statically in ways that minimise banking and maximise > reuse, based on lifetime analysis of the whole program. > > This would be a massively different way of working from how gcc does > things now, and given that such devices are very much on the decline > (when 32-bit ARM microcontrollers can be bought for 30 cents, smaller > and cheaper cpu cores are rarely the right choice for a new design), it > would not make sense to spend the effort supporting them in gcc. There > is, after all, quite a solid GPL'ed compiler toolchain for such devices > at . I think it depends on your goals. In the past I've ported GCC to a Harvard architecture system with six registers. I agree that the code quality was not the highest possible. But the port worked fine, and for this process performance was not an issue. (As you suggest, I tend to think that for most people who choose a processor with a small number of registers, performance is not an issue. Where performance matters a lot, spend the money for a real processor, or at least use a RISC/V.) Ian