From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10572 invoked by alias); 15 Nov 2016 17:37:01 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 10549 invoked by uid 89); 15 Nov 2016 17:37:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=no version=3.3.2 spammy=Hx-languages-length:704 X-HELO: mail-ua0-f182.google.com Received: from mail-ua0-f182.google.com (HELO mail-ua0-f182.google.com) (209.85.217.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Nov 2016 17:36:59 +0000 Received: by mail-ua0-f182.google.com with SMTP id 20so93616311uak.0 for ; Tue, 15 Nov 2016 09:36:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to :content-transfer-encoding; bh=7YrP0VXezQ+fqjD5MsIKhgA6XSaJesPXiVowgPmP+7s=; b=ed4rZNLAgde55OW4vR2fBz1nrWw8Svp8cb3rrmBLyw2RLty4TY/xlNQCXL3G0QqKIz YgK9TrkPShOxEcYCtiUDapZK5MSZdO3kn/cVwNl1299RNDt7b5wkkGKSvE7jqPoOuAUn 6caKGxD/1wXBruVRJMd3rHnDlvyiOdYGXrJumeGzyHop4HIKPO9qNtPAszzZMjW+aPCr byc+pw9/pTUHo1XNUbguuO1GT5UGdTKthcEtZpNTtYIwt0BNkpCH/h/w1CTRKbMKY4uw WtcFIg5qyFoWilaEWgy8HQTfetR66QweCkGV+FyDcm9Bswrw6BadTYBlUnb1cSo5hwNB 5LoQ== X-Gm-Message-State: ABUngvel667pCCqM8XRlwf0/eMdGWxWJ4C+P0sOoWIF2C0uOxmkQoZ+9+Uiqfk1VPhzUYqduxW/KfBnPxQTmyQ== X-Received: by 10.159.35.208 with SMTP id 74mr13944118uao.33.1479231417654; Tue, 15 Nov 2016 09:36:57 -0800 (PST) MIME-Version: 1.0 Received: by 10.103.126.9 with HTTP; Tue, 15 Nov 2016 09:36:27 -0800 (PST) From: Andrew Senkevich Date: Tue, 15 Nov 2016 17:37:00 -0000 Message-ID: Subject: [RFC] Support register groups in inline asm To: GCC Mailing List , Jeff Law , Kirill Yukhin Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00058.txt.bz2 Hi, new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use of register groups. To support register groups feature in inline asm needed some extension with new constraints. Current proposal is the following syntax: __asm__ (=E2=80=9CSMTH %[group], %[single]" : [single] "+x"(v= 0) : [group] "Yg4"(v1), =E2=80=9C1+1"(v2), =E2=80=9C1+2"(v3), =E2=80=9C1+3"(v4)); where "YgN" constraint specifies group of N consecutive registers (which is started from register having number as "0 mod 2^ceil(log2(N))"), and "1+K" specifies the next registers in the group. Is this syntax ok? How to implement it? Any comments or proposals will be appreciated, thanks. -- WBR, Andrew