[x86-64 psABI] RFC: Document Intel AMX

[x86-64 psABI] RFC: Document Intel AMX

[H.J. Lu]

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Intel Advanced Matrix Extensions (Intel AMX) is a new programming
paradigm consisting of two components: a set of 2-dimensional
registers (tiles) representing sub-arrays from a larger 2-dimensional
memory image, and accelerators able to operate on tiles. Capability of
Intel AMX implementation is enumerated by palettes. Two palettes are
supported: palette 0 represents the initialized state and palette 1
consists of 8 tile registers of up to 1 KB size, which is controlled
by a tile control register.

https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/12

-- 
H.J.

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From 3061010906291cd2722dc9a407dd8afe454459a5 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 6 May 2020 17:25:38 -0700
Subject: [PATCH] Document Intel AMX

Intel Advanced Matrix Extensions (Intel AMX) is a new programming
paradigm consisting of two components: a set of 2-dimensional registers
(tiles) representing sub-arrays from a larger 2-dimensional memory image,
and accelerators able to operate on tiles.  Capability of Intel AMX
implementation is enumerated by palettes.  Two palettes are supported:
palette 0 represents the initialized state and palette 1 consists of
8 tile registers of up to 1 KB size, which is controlled by a tile
control register.
---
 x86-64-ABI/low-level-sys-info.tex | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/x86-64-ABI/low-level-sys-info.tex b/x86-64-ABI/low-level-sys-info.tex
index becfa1f..2188295 100644
--- a/x86-64-ABI/low-level-sys-info.tex
+++ b/x86-64-ABI/low-level-sys-info.tex
@@ -326,6 +326,15 @@ vector register to refer to either SSE, AVX or AVX-512 register.  In
 addition, Intel AVX-512 also provides 8 vector mask registers (\reg{k0}
 - \reg{k7}), each 64-bit wide.
 
+Intel Advanced Matrix Extensions (Intel AMX) is a new programming
+paradigm consisting of two components: a set of 2-dimensional registers
+(tiles) representing sub-arrays from a larger 2-dimensional memory image,
+and accelerators able to operate on tiles.  Capability of Intel AMX
+implementation is enumerated by palettes.  Two palettes are supported:
+palette 0 represents the initialized state and palette 1 consists of
+8 tile registers (\reg{tmm0} - \reg{tmm7}) of up to 1 KB size, which
+is controlled by a tile control register.
+
 This subsection discusses usage of each register.  Registers \RBP, \RBX and
 \reg{r12} through \reg{r15} ``belong'' to the calling function and the
 called function is required to preserve their values.  In other words,
@@ -588,6 +597,7 @@ bit.}.
 \begin{figure}
 \Hrule
   \caption{Register Usage}
+  \myfontsize
   \label{fig-reg-usage}
   \begin{center}
     \begin{tabular}{l|p{7.95cm}|l}
@@ -620,6 +630,7 @@ chain pointer & No \\
 arguments & No\\
 \reg{xmm2}--\reg{xmm7} & used to pass floating point arguments & No\\
 \reg{xmm8}--\reg{xmm15} & temporary registers & No\\
+\reg{tmm0}--\reg{tmm7}& temporary registers & No\\
 \reg{mm0}--\reg{mm7}& temporary registers & No\\
 \reg{k0}--\reg{k7} & temporary registers & No\\
 \reg{st0},\reg{st1} & temporary registers, used to return \code{long double} arguments & No \\
@@ -628,6 +639,7 @@ arguments & No\\
 \code{mxcsr}& SSE2 control and status word & partial\\
 \code{x87 SW}& x87 status word & No\\
 \code{x87 CW}& x87 control word & Yes\\
+\code{tilecfig} & Tile control register & No \\
     \end{tabular}
 
   \end{center}
-- 
2.26.2