2023-10-05 Joern Rennecke gcc/ * doc/md.texi (doloop_end): Document oprional operand 2. * loop-doloop.cc (doloop_optimize): Provide 3rd operand to gen_doloop_end. * target-insns.def (doloop_end): Add optional 3rd operand. diff --git a/gcc/config.gcc b/gcc/config.gcc index ee46d96bf62..ba42ac3d425 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -544,7 +544,7 @@ riscv*) extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o" extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o" extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" - extra_objs="${extra_objs} thead.o" + extra_objs="${extra_objs} thead.o corev.o" d_target_objs="riscv-d.o" extra_headers="riscv_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" diff --git a/gcc/loop-doloop.cc b/gcc/loop-doloop.cc index 4feb0a25ab9..d703cb5f2af 100644 --- a/gcc/loop-doloop.cc +++ b/gcc/loop-doloop.cc @@ -720,7 +720,8 @@ doloop_optimize (class loop *loop) count = copy_rtx (desc->niter_expr); start_label = block_label (desc->in_edge->dest); doloop_reg = gen_reg_rtx (mode); - rtx_insn *doloop_seq = targetm.gen_doloop_end (doloop_reg, start_label); + rtx_insn *doloop_seq = targetm.gen_doloop_end (doloop_reg, start_label, + BB_END (desc->in_edge->src)); word_mode_size = GET_MODE_PRECISION (word_mode); word_mode_max = (HOST_WIDE_INT_1U << (word_mode_size - 1) << 1) - 1; @@ -737,7 +738,8 @@ doloop_optimize (class loop *loop) else count = lowpart_subreg (word_mode, count, mode); PUT_MODE (doloop_reg, word_mode); - doloop_seq = targetm.gen_doloop_end (doloop_reg, start_label); + doloop_seq = targetm.gen_doloop_end (doloop_reg, start_label, + BB_END (desc->in_edge->src)); } if (! doloop_seq) { diff --git a/gcc/target-insns.def b/gcc/target-insns.def index c4415d00735..962c5cc51d1 100644 --- a/gcc/target-insns.def +++ b/gcc/target-insns.def @@ -48,7 +48,7 @@ DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)) DEF_TARGET_INSN (check_stack, (rtx x0)) DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1)) DEF_TARGET_INSN (doloop_begin, (rtx x0, rtx x1)) -DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1)) +DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1, rtx opt2)) DEF_TARGET_INSN (eh_return, (rtx x0)) DEF_TARGET_INSN (epilogue, (void)) DEF_TARGET_INSN (exception_receiver, (void))