RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

[Peng Fan <peng.fan@nxp.com>]

Hi Michael,

> -----Original Message-----
> From: Michael Matz [mailto:matz@suse.de]
> Sent: 2019年2月13日 22:28
> To: Peng Fan <peng.fan@nxp.com>
> Cc: gcc@gcc.gnu.org; james.greenhalgh@arm.com; nd@arm.com;
> jailhouse-dev@googlegroups.com; will.deacon@arm.com; Catalin Marinas
> <catalin.marinas@arm.com>
> Subject: Re: Warning: unpredictable: identical transfer and status registers
> --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
> 
> Hi,
> 
> On Wed, 13 Feb 2019, Peng Fan wrote:
> 
> >                 asm volatile (
> >                         "ldxr   %3, %2\n\t"
> >                         "ands   %1, %3, %4\n\t"
> >                         "b.ne   1f\n\t"
> >                         "orr    %3, %3, %4\n\t"
> >                         "1:\n\t"
> >                         "stxr   %w0, %3, %2\n\t"
> >                         "dmb    ish\n\t"
> >                         : "=r" (ret), "=&r" (test),
> >                           "+Q" (*(volatile unsigned long *)addr),
> >                           "=r" (tmp)
> >                         : "r" (1ul << nr));
> 
> As Andreas says, you need to add an early-clobber for op3 for correctness (to
> force it into a different register from op4).  And you also need an
> early-clobber on op0 to force it into a different register from op2 (which for
> purposes of register assignment is an input operand holding an address).

So the fix should be the following, right?
        do {
                asm volatile (
                        "ldxr   %3, %2\n\t"
                        "ands   %1, %3, %4\n\t"
                        "b.ne   1f\n\t"
                        "orr    %3, %3, %4\n\t"
                        "1:\n\t"
                        "stxr   %w0, %3, %2\n\t"
                        "dmb    ish\n\t"
                        : "=&r" (ret), "=&r" (test),
                          "+Q" (*(volatile unsigned long *)addr),
                          "=&r" (tmp)
                        : "r" (1ul << nr));
        } while (ret);

Thanks,
Peng.

> 
> 
> Ciao,
> Michael.