From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 823 invoked by alias); 8 Jan 2003 05:27:38 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 515 invoked from network); 8 Jan 2003 05:25:05 -0000 Received: from unknown (HELO falcon.mail.pas.earthlink.net) (207.217.120.74) by 209.249.29.67 with SMTP; 8 Jan 2003 05:25:05 -0000 Received: from ilmasc01-61.midwest.net ([209.248.16.71] helo=there) by falcon.mail.pas.earthlink.net with smtp (Exim 3.33 #1) id 18W8hk-0002fO-00; Tue, 07 Jan 2003 21:24:40 -0800 Content-Type: text/plain; charset="iso-8859-1" From: Andy Walker To: Michael S. Zick , dewar@gnat.com (Robert Dewar), velco@fadata.bg Subject: Re: An unusual Performance approach using Synthetic registers Date: Wed, 08 Jan 2003 06:56:00 -0000 Cc: gcc@gcc.gnu.org, lord@emf.net References: <20030107124729.AAD0EF28E5@nile.gnat.com> <03010710182700.00736@localhost.localdomain> In-Reply-To: <03010710182700.00736@localhost.localdomain> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Message-Id: X-SW-Source: 2003-01/txt/msg00404.txt.bz2 On Tuesday 07 January 2003 10:18 am, Michael S. Zick wrote: > On Tuesday 07 January 2003 06:47 am, Robert Dewar wrote: > > I had thought that these instructions were only available on recent > > chips, so if they are used you have to be careful about back > > compatibility. > > Good advice; > Andy, you mentioned your machine was a "Pentium" (without any > qualifications) so your machine doesn't have prefetch instructions. > > Momchil Velikov gave a nice list in his post. > > The exchange (xchg) instruction was included in the original 80386. > It also issued a "bus lock" signal from the chip but as time passed, > problems where found with its timing and its use for atomically handling > symiphores was replaced with new instructions for that purpose. > > It has always done its register <-> memory thing correctly. Thank you for the info. This is _not_ in the XCHG description in the Intel Developer's manuals. My point, however, was that XCHG causes unavoidable processor locks in register-memory form. This is unacceptable for any instruction used to speed up straight computation. I passed on using it. > Also, your "Pentium" (without any qualifications) does not have the > "out of order execution, with register renaming, in multiple execution > units" grown into its silcon. Just ignore us on that subject. ok. for now. :o) dumb statistic, fwiw: dual processor 500Mhz Celerons. My Mandrake 8.2 distro calls it a pentiumpro. > The easy way is to just keep on asking the list, some of us > have been writing Intel-ASM since the I-4004 hit the > street. (Myself included.) > > Mike I will. Thank you for the invitation. Andy