From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12030 invoked by alias); 19 Mar 2004 18:57:41 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 12016 invoked from network); 19 Mar 2004 18:57:39 -0000 Received: from unknown (HELO mail-out3.apple.com) (17.254.13.22) by sources.redhat.com with SMTP; 19 Mar 2004 18:57:39 -0000 Received: from mailgate1.apple.com (a17-128-100-225.apple.com [17.128.100.225]) by mail-out3.apple.com (8.12.11/8.12.11) with ESMTP id i2JIvdF1011461 for ; Fri, 19 Mar 2004 10:57:39 -0800 (PST) Received: from relay2.apple.com (relay2.apple.com) by mailgate1.apple.com (Content Technologies SMTPRS 4.3.6) with ESMTP id ; Fri, 19 Mar 2004 10:57:38 -0800 Received: from [17.201.20.186] (gambrinus.apple.com [17.201.20.186]) by relay2.apple.com (8.12.11/8.12.11) with ESMTP id i2JIvLoM000977; Fri, 19 Mar 2004 18:57:22 GMT In-Reply-To: References: Mime-Version: 1.0 (Apple Message framework v612) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: Content-Transfer-Encoding: 7bit Cc: gcc@gcc.gnu.org, David Edelsohn , Dale Johannesen From: Dale Johannesen Subject: Re: rs6000.md/altivec.md problem in setting of vector registers Date: Fri, 19 Mar 2004 20:59:00 -0000 To: Dorit Naishlos X-SW-Source: 2004-03/txt/msg01163.txt.bz2 On Mar 18, 2004, at 4:52 PM, Dorit Naishlos wrote: > I managed to hack something that causes Reload to make the "right" > decision > and generate the same code as it generates for i386 - i.e., the spill > code > is created out of the loop. > > The hack modifies the macro CANNOT_CHANGE_MODE_CLASS in rs6000.h to not > allow a mode change from a vector mode to a smaller mode in > ALTIVEC_REGS or > GENERAL_REGS. As a result, these register classes cannot be considered > for > allocation in this case; instead, Reload directly creates stores to > memory, > outside the loop, like for i386. I haven't tried it, but this might well break passing of vector parameters in int regs.