From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31958 invoked by alias); 29 Nov 2004 18:35:26 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 31585 invoked from network); 29 Nov 2004 18:35:18 -0000 Received: from unknown (HELO NUTMEG.CAM.ARTIMI.COM) (217.40.111.177) by sourceware.org with SMTP; 29 Nov 2004 18:35:18 -0000 Received: from mace ([192.168.1.25]) by NUTMEG.CAM.ARTIMI.COM with Microsoft SMTPSVC(6.0.3790.211); Mon, 29 Nov 2004 18:33:52 +0000 From: "Dave Korn" To: "'Peter Barada'" , Cc: , , Subject: RE: warning: right shift count >= width of type Date: Mon, 29 Nov 2004 18:53:00 -0000 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit In-Reply-To: <20041129180903.5C5E79842C@baradas.org> Message-ID: X-OriginalArrivalTime: 29 Nov 2004 18:33:52.0062 (UTC) FILETIME=[F9841DE0:01C4D641] X-SW-Source: 2004-11/txt/msg01148.txt.bz2 > -----Original Message----- > From: Peter Barada > Sent: 29 November 2004 18:09 > > > ISTM reasonable that the result of a right-shift by 32 bits could > > > be assumed to be the same thing you get if you > right-shift by 1 bit > > > 32 times.... > > > >The chip designers don't agree. > > They *definitely* don't agree. Most shift hardware is designed as a > barrel shifter which is a large combinational logic block > that takes the > n-bits of the shift count and using them determine what each bit of > the result is supposed to be. This allows a shift that takes only one > clock, wheter the shift is arithmetic or logical, right or left, and a > shift count from 0 up to the number of bits in the register-1. > > Any shift count outside of that range is considered "undefined". No, I think it's more accurate to say that any shift count outside that range is *unimplemented*. "Undefined" is a concept from the C language standard; mathematically, the operation is well defined, and in a practical physical implementation, the operation is either "implemented" or "unimplemented", but either way can hardly fail to be "defined", owing to the deterministic nature of hardware implementations. > n 1-bit shifts is equivient to 1 n-bit shift only if n is less than > the size of the register in bits, at least for a hardware > implementation described above. Similarly, I would say that 1 n-bit shift simply cannot be expressed on such hardware, and it is meaningless to compare the outcome of a series of operations that exist with some entirely hypothetical outcome of an operation that simply does *not* exist. cheers, DaveK -- Can't think of a witty .sigline today....