* Solve transitive closure issue in modulo scheduling
@ 2009-01-30 16:17 Bingfeng Mei
2009-02-01 23:18 ` Ayal Zaks
2009-02-07 17:20 ` Solve transitive closure issue in modulo scheduling Daniel Berlin
0 siblings, 2 replies; 10+ messages in thread
From: Bingfeng Mei @ 2009-01-30 16:17 UTC (permalink / raw)
To: gcc, zaks; +Cc: Adrian Ashley
Hello,
I try to make modulo scheduling work more efficiently for our VLIW target. I found one serious issue that prevents current SMS algorithm from achieving high IPC is so-called "transitive closure" problem, where scheduling window is only calculated using direct predecessors and successors. Because SMS is not an iterative algorithm, this may cause failures in finding a valid schedule. Without splitting rows, some simple loops just cannot be scheduled not matter how big the II is. With splitting rows, schedule can be found, but only at bigger II. GCC wiki (http://gcc.gnu.org/wiki/SwingModuloScheduling) lists this as a TODO. Is there any work going on about this issue (the last wiki update was one year ago)? If no one is working on it, I plan to do it. My idea is to use the MinDist algorithm described in B. Rau's classic paper "iterative modulo scheduling" (http://www.hpl.hp.com/techreports/94/HPL-94-115.html). The same algorithm can also be used to compute better RecMII. The biggest concern is complexity of computing MinDist matrix, which is O(N^3). N is number of nodes in the loop. I remember somewhere GCC coding guide says "never write quadratic algorithm" :-) Is this an absolute requirement? If yes, I will keep it as our target-specific code (we are less concerned about compilation time). Otherwise, I will try to make it more generic to see if it can make into mainline in 4.5. Any comments?
Cheers,
Bingfeng Mei
Broadcom UK
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Solve transitive closure issue in modulo scheduling
2009-01-30 16:17 Solve transitive closure issue in modulo scheduling Bingfeng Mei
@ 2009-02-01 23:18 ` Ayal Zaks
2009-02-05 10:45 ` Bingfeng Mei
2009-02-07 17:20 ` Solve transitive closure issue in modulo scheduling Daniel Berlin
1 sibling, 1 reply; 10+ messages in thread
From: Ayal Zaks @ 2009-02-01 23:18 UTC (permalink / raw)
To: Bingfeng Mei; +Cc: Adrian Ashley, gcc
"Bingfeng Mei" <bmei@broadcom.com> wrote on 30/01/2009 14:44:01:
> Hello,
> I try to make modulo scheduling work more efficiently for our VLIW
target. I
> found one serious issue that prevents current SMS algorithm from
achieving
> high IPC is so-called "transitive closure" problem, where scheduling
window is
> only calculated using direct predecessors and successors. Because SMS is
not
> an iterative algorithm, this may cause failures in finding a valid
schedule.
Agreed.
> Without splitting rows, some simple loops just cannot be scheduled not
matter
> how big the II is. With splitting rows, schedule can be found, but only
at
> bigger II.
It may happen that even splitting rows will not help, e.g. when we
repeatedly end up with a node having negative sched window.
> GCC wiki (http://gcc.gnu.org/wiki/SwingModuloScheduling) lists this
> as a TODO. Is there any work going on about this issue
No, not to my knowledge. We had some testcase where this showed up, hence
its appearance in the TODO, but afaicr some change caused it to disappear.
> (the last wiki update
> was one year ago)? If no one is working on it, I plan to do it. My idea
is to
> use the MinDist algorithm described in B. Rau's classic paper "iterative
> modulo
scheduling" (http://www.hpl.hp.com/techreports/94/HPL-94-115.html). The
> same algorithm can also be used to compute better RecMII. The biggest
concern
> is complexity of computing MinDist matrix, which is O(N^3). N is number
of
> nodes in the loop. I remember somewhere GCC coding guide says "never
write
> quadratic algorithm" :-) Is this an absolute requirement? If yes, I will
keep
> it as our target-specific code (we are less concerned about compilation
time).
> Otherwise, I will try to make it more generic to see if it can make into
> mainline in 4.5. Any comments?
>
The problem appears only when the DDG is cyclic, and for every cycle in the
DDG, the problem may arise when trying to schedule the last node of the
cycle, which has both predecessors and successors already scheduled. So you
might try to connect only each such predecessor to every such successor
with a transitive arc, to ensure that this last node will have a non-empty
scheduling window. But this might not suffice; you may eventually need to
wire (nearly) every pair of nodes in the strongly connected component. If
this happens, you'd be better off with a dense graph representation
(incidence matrix) than the current sparse one (adjaceny lists).
An example would help see things more clearly. If you have a (small :) DDG
demonstrating the need for transitive arcs, I'd be happy to have a look and
advise what should be done.
Ayal.
> Cheers,
> Bingfeng Mei
>
> Broadcom UK
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: Solve transitive closure issue in modulo scheduling
2009-02-01 23:18 ` Ayal Zaks
@ 2009-02-05 10:45 ` Bingfeng Mei
2009-02-17 12:03 ` Ayal Zaks
0 siblings, 1 reply; 10+ messages in thread
From: Bingfeng Mei @ 2009-02-05 10:45 UTC (permalink / raw)
To: Ayal Zaks; +Cc: Adrian Ashley, gcc
[-- Attachment #1: Type: text/plain, Size: 4154 bytes --]
Ayal,
OOPs, your mail skipped my inbox and I missed it for several days.
Using testsuite/gcc.dg/sms-6.c as an example and compiling it for PowerPC, node 18 (see attachment) is in a SCC and cannot be scheduled until spliting twice. The MII = 20 and the schedule can only be found at II = 24. On our 2-issue VLIW, the MII=10 and the valid schedule can only be found at II = 14. It is not great since we want to maximize performance.
I had experience (in development of another compiler) on this issue by constructing the MinDist matrix and using it to calculate schedule window for each instruction. However, speed was not a real concern then. Do you know better algorithm (better than O(N^3))? Or do you think it is not so crtical here? After all, not many loops are candidates for software pipelining. Thanks.
Cheers,
Bingfeng
> -----Original Message-----
> From: gcc-owner@gcc.gnu.org [mailto:gcc-owner@gcc.gnu.org] On
> Behalf Of Ayal Zaks
> Sent: 01 February 2009 23:18
> To: Bingfeng Mei
> Cc: Adrian Ashley; gcc@gcc.gnu.org
> Subject: Re: Solve transitive closure issue in modulo scheduling
>
> "Bingfeng Mei" <bmei@broadcom.com> wrote on 30/01/2009 14:44:01:
>
> > Hello,
> > I try to make modulo scheduling work more efficiently for our VLIW
> target. I
> > found one serious issue that prevents current SMS algorithm from
> achieving
> > high IPC is so-called "transitive closure" problem, where scheduling
> window is
> > only calculated using direct predecessors and successors.
> Because SMS is
> not
> > an iterative algorithm, this may cause failures in finding a valid
> schedule.
>
> Agreed.
>
> > Without splitting rows, some simple loops just cannot be
> scheduled not
> matter
> > how big the II is. With splitting rows, schedule can be
> found, but only
> at
> > bigger II.
>
> It may happen that even splitting rows will not help, e.g. when we
> repeatedly end up with a node having negative sched window.
>
> > GCC wiki (http://gcc.gnu.org/wiki/SwingModuloScheduling) lists this
> > as a TODO. Is there any work going on about this issue
>
> No, not to my knowledge. We had some testcase where this
> showed up, hence
> its appearance in the TODO, but afaicr some change caused it
> to disappear.
>
> > (the last wiki update
> > was one year ago)? If no one is working on it, I plan to do
> it. My idea
> is to
> > use the MinDist algorithm described in B. Rau's classic
> paper "iterative
> > modulo
> scheduling"
> (http://www.hpl.hp.com/techreports/94/HPL-94-115.html). The
> > same algorithm can also be used to compute better RecMII.
> The biggest
> concern
> > is complexity of computing MinDist matrix, which is O(N^3).
> N is number
> of
> > nodes in the loop. I remember somewhere GCC coding guide says "never
> write
> > quadratic algorithm" :-) Is this an absolute requirement?
> If yes, I will
> keep
> > it as our target-specific code (we are less concerned about
> compilation
> time).
> > Otherwise, I will try to make it more generic to see if it
> can make into
> > mainline in 4.5. Any comments?
> >
>
> The problem appears only when the DDG is cyclic, and for
> every cycle in the
> DDG, the problem may arise when trying to schedule the last
> node of the
> cycle, which has both predecessors and successors already
> scheduled. So you
> might try to connect only each such predecessor to every such
> successor
> with a transitive arc, to ensure that this last node will
> have a non-empty
> scheduling window. But this might not suffice; you may
> eventually need to
> wire (nearly) every pair of nodes in the strongly connected
> component. If
> this happens, you'd be better off with a dense graph representation
> (incidence matrix) than the current sparse one (adjaceny lists).
>
> An example would help see things more clearly. If you have a
> (small :) DDG
> demonstrating the need for transitive arcs, I'd be happy to
> have a look and
> advise what should be done.
>
> Ayal.
>
> > Cheers,
> > Bingfeng Mei
> >
> > Broadcom UK
> >
> >
>
>
>
[-- Attachment #2: sms-6.c.169r.sms --]
[-- Type: application/octet-stream, Size: 120770 bytes --]
;; Function foo (foo)
try_optimize_cfg iteration 1
;; 2 loops found
;;
;; Loop 0
;; header 0, latch 1
;; depth 0, outer -1
;; nodes: 0 1 2 3 4
;;
;; Loop 1
;; header 3, latch 3
;; depth 1, outer 0
;; nodes: 3
;; 2 succs { 3 }
;; 3 succs { 3 4 }
;; 4 succs { 1 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 8 ( 1.6)
SMS analysis phase
===================
SMS loop num: 1, file: sms-6.c, line: 9
...OK
SMS transformation phase
=========================
SMS loop num: 1, file: sms-6.c, line: 9
Node num: 0
(insn:HI 48 47 49 3 sms-6.c:11 (set (reg:SI 161)
(mem:SI (reg/f:SI 156 [ ivtmp.42 ]) [4 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [48 -(A,0,0)-> 65] [48 -(T,2,0)-> 50]
IN ARCS: [50 -(A,0,1)-> 48] [65 -(T,1,1)-> 48]
Node num: 1
(insn:HI 49 48 50 3 sms-6.c:11 (set (reg:SI 162)
(mem:SI (reg/f:SI 157 [ ivtmp.40 ]) [5 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [49 -(A,0,0)-> 64] [49 -(T,2,0)-> 50]
IN ARCS: [50 -(A,0,1)-> 49] [64 -(T,1,1)-> 49]
Node num: 2
(insn:HI 50 49 51 3 sms-6.c:11 (set (reg:SI 163)
(mult:SI (reg:SI 161)
(reg:SI 162))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 162)
(expr_list:REG_DEAD (reg:SI 161)
(nil))))
OUT ARCS: [50 -(A,0,1)-> 49] [50 -(A,0,1)-> 48] [50 -(T,4,0)-> 51]
IN ARCS: [51 -(A,0,1)-> 50] [48 -(T,2,0)-> 50] [49 -(T,2,0)-> 50]
Node num: 3
(insn:HI 51 50 52 3 sms-6.c:11 (set (mem:SI (reg/f:SI 155 [ ivtmp.43 ]) [3 S4 A32])
(reg:SI 163)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 163)
(nil)))
OUT ARCS: [51 -(A,0,1)-> 50] [51 -(O,0,0)-> 85] [51 -(A,0,0)-> 66]
IN ARCS: [66 -(T,1,1)-> 51] [63 -(O,0,1)-> 51] [59 -(O,0,1)-> 51] [55 -(O,0,1)-> 51] [50 -(T,4,0)-> 51]
Node num: 4
(insn:HI 52 51 53 3 sms-6.c:12 (set (reg:SI 164)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 4 [0x4])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [52 -(A,0,0)-> 65] [52 -(T,2,0)-> 54]
IN ARCS: [54 -(A,0,1)-> 52] [65 -(T,1,1)-> 52]
Node num: 5
(insn:HI 53 52 54 3 sms-6.c:12 (set (reg:SI 165)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 4 [0x4])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [53 -(A,0,0)-> 64] [53 -(T,2,0)-> 54]
IN ARCS: [54 -(A,0,1)-> 53] [64 -(T,1,1)-> 53]
Node num: 6
(insn:HI 54 53 55 3 sms-6.c:12 (set (reg:SI 166)
(mult:SI (reg:SI 164)
(reg:SI 165))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 165)
(expr_list:REG_DEAD (reg:SI 164)
(nil))))
OUT ARCS: [54 -(A,0,1)-> 53] [54 -(A,0,1)-> 52] [54 -(T,4,0)-> 55]
IN ARCS: [55 -(A,0,1)-> 54] [52 -(T,2,0)-> 54] [53 -(T,2,0)-> 54]
Node num: 7
(insn:HI 55 54 56 3 sms-6.c:12 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 166)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 166)
(nil)))
OUT ARCS: [55 -(A,0,1)-> 54] [55 -(O,0,0)-> 85] [55 -(A,0,0)-> 66] [55 -(O,0,1)-> 51]
IN ARCS: [66 -(T,1,1)-> 55] [63 -(O,0,1)-> 55] [59 -(O,0,1)-> 55] [54 -(T,4,0)-> 55]
Node num: 8
(insn:HI 56 55 57 3 sms-6.c:13 (set (reg:SI 167)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 8 [0x8])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [56 -(A,0,0)-> 65] [56 -(T,2,0)-> 58]
IN ARCS: [58 -(A,0,1)-> 56] [65 -(T,1,1)-> 56]
Node num: 9
(insn:HI 57 56 58 3 sms-6.c:13 (set (reg:SI 168)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 8 [0x8])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [57 -(A,0,0)-> 64] [57 -(T,2,0)-> 58]
IN ARCS: [58 -(A,0,1)-> 57] [64 -(T,1,1)-> 57]
Node num: 10
(insn:HI 58 57 59 3 sms-6.c:13 (set (reg:SI 169)
(mult:SI (reg:SI 167)
(reg:SI 168))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 168)
(expr_list:REG_DEAD (reg:SI 167)
(nil))))
OUT ARCS: [58 -(A,0,1)-> 57] [58 -(A,0,1)-> 56] [58 -(T,4,0)-> 59]
IN ARCS: [59 -(A,0,1)-> 58] [56 -(T,2,0)-> 58] [57 -(T,2,0)-> 58]
Node num: 11
(insn:HI 59 58 60 3 sms-6.c:13 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 169)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 169)
(nil)))
OUT ARCS: [59 -(A,0,1)-> 58] [59 -(O,0,0)-> 85] [59 -(A,0,0)-> 66] [59 -(O,0,1)-> 55] [59 -(O,0,1)-> 51]
IN ARCS: [66 -(T,1,1)-> 59] [63 -(O,0,1)-> 59] [58 -(T,4,0)-> 59]
Node num: 12
(insn:HI 60 59 61 3 sms-6.c:14 (set (reg:SI 170)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 12 [0xc])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [60 -(A,0,0)-> 65] [60 -(T,2,0)-> 62]
IN ARCS: [62 -(A,0,1)-> 60] [65 -(T,1,1)-> 60]
Node num: 13
(insn:HI 61 60 62 3 sms-6.c:14 (set (reg:SI 171)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 12 [0xc])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [61 -(A,0,0)-> 64] [61 -(T,2,0)-> 62]
IN ARCS: [62 -(A,0,1)-> 61] [64 -(T,1,1)-> 61]
Node num: 14
(insn:HI 62 61 63 3 sms-6.c:14 (set (reg:SI 172)
(mult:SI (reg:SI 170)
(reg:SI 171))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 171)
(expr_list:REG_DEAD (reg:SI 170)
(nil))))
OUT ARCS: [62 -(A,0,1)-> 61] [62 -(A,0,1)-> 60] [62 -(T,4,0)-> 63]
IN ARCS: [63 -(A,0,1)-> 62] [60 -(T,2,0)-> 62] [61 -(T,2,0)-> 62]
Node num: 15
(insn:HI 63 62 64 3 sms-6.c:14 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 172)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 172)
(nil)))
OUT ARCS: [63 -(A,0,1)-> 62] [63 -(O,0,0)-> 85] [63 -(A,0,0)-> 66] [63 -(O,0,1)-> 59] [63 -(O,0,1)-> 55] [63 -(O,0,1)-> 51]
IN ARCS: [66 -(T,1,1)-> 63] [62 -(T,4,0)-> 63]
Node num: 16
(insn:HI 64 63 65 3 sms-6.c:14 (set (reg/f:SI 157 [ ivtmp.40 ])
(plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
OUT ARCS: [64 -(T,1,1)-> 49] [64 -(T,1,1)-> 53] [64 -(T,1,1)-> 57] [64 -(T,1,1)-> 61] [64 -(T,1,1)-> 64]
IN ARCS: [64 -(T,1,1)-> 64] [61 -(A,0,0)-> 64] [57 -(A,0,0)-> 64] [53 -(A,0,0)-> 64] [49 -(A,0,0)-> 64]
Node num: 17
(insn:HI 65 64 66 3 sms-6.c:14 (set (reg/f:SI 156 [ ivtmp.42 ])
(plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
OUT ARCS: [65 -(T,1,1)-> 48] [65 -(T,1,1)-> 52] [65 -(T,1,1)-> 56] [65 -(T,1,1)-> 60] [65 -(T,1,1)-> 65]
IN ARCS: [65 -(T,1,1)-> 65] [60 -(A,0,0)-> 65] [56 -(A,0,0)-> 65] [52 -(A,0,0)-> 65] [48 -(A,0,0)-> 65]
Node num: 18
(insn:HI 66 65 85 3 sms-6.c:14 (set (reg/f:SI 155 [ ivtmp.43 ])
(plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
OUT ARCS: [66 -(T,1,1)-> 51] [66 -(T,1,1)-> 55] [66 -(T,1,1)-> 59] [66 -(T,1,1)-> 63] [66 -(T,1,1)-> 66]
IN ARCS: [66 -(T,1,1)-> 66] [63 -(A,0,0)-> 66] [59 -(A,0,0)-> 66] [55 -(A,0,0)-> 66] [51 -(A,0,0)-> 66]
Node num: 19
(jump_insn:HI 85 66 77 3 sms-6.c:9 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 174)
(const_int 1 [0x1]))
(label_ref:SI 67)
(pc)))
(set (reg:SI 174)
(plus:SI (reg:SI 174)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9600 [0x2580])
(nil)))
OUT ARCS: [85 -(T,1,1)-> 85] [85 -(T,1,1)-> 85]
IN ARCS: [85 -(T,1,1)-> 85] [85 -(T,1,1)-> 85] [63 -(O,0,0)-> 85] [59 -(O,0,0)-> 85] [55 -(O,0,0)-> 85] [51 -(O,0,0)-> 85]
sms-6.c 9 (file, line)
SMS single-bb-loop
SMS doloop
SMS built-ddg 20
SMS num-loads 8
SMS num-stores 4
SMS const-doloop 25
Order params
node 0, ASAP: 0, ALAP: 0, HEIGHT: 6
node 1, ASAP: 0, ALAP: 0, HEIGHT: 6
node 2, ASAP: 2, ALAP: 2, HEIGHT: 4
node 3, ASAP: 6, ALAP: 6, HEIGHT: 0
node 4, ASAP: 0, ALAP: 0, HEIGHT: 6
node 5, ASAP: 0, ALAP: 0, HEIGHT: 6
node 6, ASAP: 2, ALAP: 2, HEIGHT: 4
node 7, ASAP: 6, ALAP: 6, HEIGHT: 0
node 8, ASAP: 0, ALAP: 0, HEIGHT: 6
node 9, ASAP: 0, ALAP: 0, HEIGHT: 6
node 10, ASAP: 2, ALAP: 2, HEIGHT: 4
node 11, ASAP: 6, ALAP: 6, HEIGHT: 0
node 12, ASAP: 0, ALAP: 0, HEIGHT: 6
node 13, ASAP: 0, ALAP: 0, HEIGHT: 6
node 14, ASAP: 2, ALAP: 2, HEIGHT: 4
node 15, ASAP: 6, ALAP: 6, HEIGHT: 0
node 16, ASAP: 0, ALAP: 6, HEIGHT: 0
node 17, ASAP: 0, ALAP: 6, HEIGHT: 0
node 18, ASAP: 6, ALAP: 6, HEIGHT: 0
node 19, ASAP: 6, ALAP: 6, HEIGHT: 0
;; Number of SCC nodes - 2
SCC number: 0
insn num 0
(insn:HI 48 47 49 3 sms-6.c:11 (set (reg:SI 161)
(mem:SI (reg/f:SI 156 [ ivtmp.42 ]) [4 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 1
(insn:HI 49 48 50 3 sms-6.c:11 (set (reg:SI 162)
(mem:SI (reg/f:SI 157 [ ivtmp.40 ]) [5 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 2
(insn:HI 50 49 51 3 sms-6.c:11 (set (reg:SI 163)
(mult:SI (reg:SI 161)
(reg:SI 162))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 162)
(expr_list:REG_DEAD (reg:SI 161)
(nil))))
insn num 3
(insn:HI 51 50 52 3 sms-6.c:11 (set (mem:SI (reg/f:SI 155 [ ivtmp.43 ]) [3 S4 A32])
(reg:SI 163)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 163)
(nil)))
insn num 4
(insn:HI 52 51 53 3 sms-6.c:12 (set (reg:SI 164)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 4 [0x4])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 5
(insn:HI 53 52 54 3 sms-6.c:12 (set (reg:SI 165)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 4 [0x4])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 6
(insn:HI 54 53 55 3 sms-6.c:12 (set (reg:SI 166)
(mult:SI (reg:SI 164)
(reg:SI 165))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 165)
(expr_list:REG_DEAD (reg:SI 164)
(nil))))
insn num 7
(insn:HI 55 54 56 3 sms-6.c:12 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 166)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 166)
(nil)))
insn num 8
(insn:HI 56 55 57 3 sms-6.c:13 (set (reg:SI 167)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 8 [0x8])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 9
(insn:HI 57 56 58 3 sms-6.c:13 (set (reg:SI 168)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 8 [0x8])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 10
(insn:HI 58 57 59 3 sms-6.c:13 (set (reg:SI 169)
(mult:SI (reg:SI 167)
(reg:SI 168))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 168)
(expr_list:REG_DEAD (reg:SI 167)
(nil))))
insn num 11
(insn:HI 59 58 60 3 sms-6.c:13 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 169)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 169)
(nil)))
insn num 12
(insn:HI 60 59 61 3 sms-6.c:14 (set (reg:SI 170)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 12 [0xc])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 13
(insn:HI 61 60 62 3 sms-6.c:14 (set (reg:SI 171)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 12 [0xc])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
insn num 14
(insn:HI 62 61 63 3 sms-6.c:14 (set (reg:SI 172)
(mult:SI (reg:SI 170)
(reg:SI 171))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 171)
(expr_list:REG_DEAD (reg:SI 170)
(nil))))
insn num 15
(insn:HI 63 62 64 3 sms-6.c:14 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 172)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 172)
(nil)))
insn num 16
(insn:HI 64 63 65 3 sms-6.c:14 (set (reg/f:SI 157 [ ivtmp.40 ])
(plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
insn num 17
(insn:HI 65 64 66 3 sms-6.c:14 (set (reg/f:SI 156 [ ivtmp.42 ])
(plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
insn num 18
(insn:HI 66 65 85 3 sms-6.c:14 (set (reg/f:SI 155 [ ivtmp.43 ])
(plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
SCC number: 1
insn num 19
(jump_insn:HI 85 66 77 3 sms-6.c:9 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 174)
(const_int 1 [0x1]))
(label_ref:SI 67)
(pc)))
(set (reg:SI 174)
(plus:SI (reg:SI 174)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9600 [0x2580])
(nil)))
SMS final nodes order:
3 7 11 15 18 2 6 10 14 0 1 4 5 8 9 12 13 16 17 19
SMS iis 4 20 40 (rec_mii, mii, maxii)
Starting with ii=20
Trying to schedule node 3 INSN = 51 in (6 .. 26) step 1
must_precede:
must_follow:
Scheduled w/o split in 6
Processing edge: [55 -(A,0,1)-> 54]
Scheduling 7 (55) in pss_not_empty, checking s 6 (54): the node is not scheduled
Processing edge: [55 -(O,0,0)-> 85]
Scheduling 7 (55) in pss_not_empty, checking s 19 (85): the node is not scheduled
Processing edge: [55 -(A,0,0)-> 66]
Scheduling 7 (55) in pss_not_empty, checking s 18 (66): the node is not scheduled
Processing edge: [55 -(O,0,1)-> 51]
Scheduling 7 (55) in pss_not_empty, checking s 3 (51): succ st = 6; late_start = 26; latency = 0end = -13
Scheduling 7 (55) in a window (26..6) with step -1
Trying to schedule node 7 INSN = 55 in (26 .. 6) step -1
must_precede:
must_follow: 3
Scheduled w/o split in 25
Processing edge: [59 -(A,0,1)-> 58]
Scheduling 11 (59) in pss_not_empty, checking s 10 (58): the node is not scheduled
Processing edge: [59 -(O,0,0)-> 85]
Scheduling 11 (59) in pss_not_empty, checking s 19 (85): the node is not scheduled
Processing edge: [59 -(A,0,0)-> 66]
Scheduling 11 (59) in pss_not_empty, checking s 18 (66): the node is not scheduled
Processing edge: [59 -(O,0,1)-> 55]
Scheduling 11 (59) in pss_not_empty, checking s 7 (55): succ st = 25; late_start = 45; latency = 0end = 6
Processing edge: [59 -(O,0,1)-> 51]
Scheduling 11 (59) in pss_not_empty, checking s 3 (51): succ st = 6; late_start = 26; latency = 0end = 6
Scheduling 11 (59) in a window (26..6) with step -1
Trying to schedule node 11 INSN = 59 in (26 .. 6) step -1
must_precede:
must_follow: 3
Scheduled w/o split in 24
Processing edge: [63 -(A,0,1)-> 62]
Scheduling 15 (63) in pss_not_empty, checking s 14 (62): the node is not scheduled
Processing edge: [63 -(O,0,0)-> 85]
Scheduling 15 (63) in pss_not_empty, checking s 19 (85): the node is not scheduled
Processing edge: [63 -(A,0,0)-> 66]
Scheduling 15 (63) in pss_not_empty, checking s 18 (66): the node is not scheduled
Processing edge: [63 -(O,0,1)-> 59]
Scheduling 15 (63) in pss_not_empty, checking s 11 (59): succ st = 24; late_start = 44; latency = 0end = 5
Processing edge: [63 -(O,0,1)-> 55]
Scheduling 15 (63) in pss_not_empty, checking s 7 (55): succ st = 25; late_start = 44; latency = 0end = 6
Processing edge: [63 -(O,0,1)-> 51]
Scheduling 15 (63) in pss_not_empty, checking s 3 (51): succ st = 6; late_start = 26; latency = 0end = 6
Scheduling 15 (63) in a window (26..6) with step -1
Trying to schedule node 15 INSN = 63 in (26 .. 6) step -1
must_precede:
must_follow: 3
Scheduled w/o split in 23
Processing edge: [66 -(T,1,1)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 18 (66): the node is not scheduled
Processing edge: [63 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 15 (63): pred st = 23; early_start = 23; latency = 0
Processing edge: [59 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 11 (59): pred st = 24; early_start = 24; latency = 0
Processing edge: [55 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 7 (55): pred st = 25; early_start = 25; latency = 0
Processing edge: [51 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 3 (51): pred st = 6; early_start = 25; latency = 0
Processing edge: [66 -(T,1,1)-> 51]
Scheduling 18 (66) in psp_pss_not_empty, checking s 3 (51): succ st = 6; late_start = 25; latency = 1
Processing edge: [66 -(T,1,1)-> 55]
Scheduling 18 (66) in psp_pss_not_empty, checking s 7 (55): succ st = 25; late_start = 25; latency = 1
Processing edge: [66 -(T,1,1)-> 59]
Scheduling 18 (66) in psp_pss_not_empty, checking s 11 (59): succ st = 24; late_start = 25; latency = 1
Processing edge: [66 -(T,1,1)-> 63]
Scheduling 18 (66) in psp_pss_not_empty, checking s 15 (63): succ st = 23; late_start = 25; latency = 1
Processing edge: [66 -(T,1,1)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking s 18 (66): the node is not scheduled
Trying to schedule node 18 INSN = 66 in (25 .. 24) step -1
must_precede: 7
must_follow:
split_row=19
crr_insn->node=15, crr_insn->cycle=23, min_cycle=6
crr_insn->node=11, crr_insn->cycle=24, min_cycle=6
crr_insn->node=7, crr_insn->cycle=25, min_cycle=6
crr_insn->node=3, crr_insn->cycle=6, min_cycle=6
min_cycle=0, max_cycle=20
num_splits=1
Processing edge: [66 -(T,1,1)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 18 (66): the node is not scheduled
Processing edge: [63 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 15 (63): pred st = 17; early_start = 17; latency = 0
Processing edge: [59 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 11 (59): pred st = 18; early_start = 18; latency = 0
Processing edge: [55 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 7 (55): pred st = 20; early_start = 20; latency = 0
Processing edge: [51 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 3 (51): pred st = 0; early_start = 20; latency = 0
Processing edge: [66 -(T,1,1)-> 51]
Scheduling 18 (66) in psp_pss_not_empty, checking s 3 (51): succ st = 0; late_start = 20; latency = 1
Processing edge: [66 -(T,1,1)-> 55]
Scheduling 18 (66) in psp_pss_not_empty, checking s 7 (55): succ st = 20; late_start = 20; latency = 1
Processing edge: [66 -(T,1,1)-> 59]
Scheduling 18 (66) in psp_pss_not_empty, checking s 11 (59): succ st = 18; late_start = 20; latency = 1
Processing edge: [66 -(T,1,1)-> 63]
Scheduling 18 (66) in psp_pss_not_empty, checking s 15 (63): succ st = 17; late_start = 20; latency = 1
Processing edge: [66 -(T,1,1)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking s 18 (66): the node is not scheduled
Trying to schedule node 18 INSN = 66 in (20 .. 19) step -1
must_precede: 7
must_follow:
split_row=0
crr_insn->node=3, crr_insn->cycle=0, min_cycle=0
crr_insn->node=15, crr_insn->cycle=17, min_cycle=0
crr_insn->node=11, crr_insn->cycle=18, min_cycle=0
crr_insn->node=7, crr_insn->cycle=20, min_cycle=0
min_cycle=1, max_cycle=21
num_splits=2
Processing edge: [66 -(T,1,1)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 18 (66): the node is not scheduled
Processing edge: [63 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 15 (63): pred st = 18; early_start = 18; latency = 0
Processing edge: [59 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 11 (59): pred st = 19; early_start = 19; latency = 0
Processing edge: [55 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 7 (55): pred st = 21; early_start = 21; latency = 0
Processing edge: [51 -(A,0,0)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking p 3 (51): pred st = 1; early_start = 21; latency = 0
Processing edge: [66 -(T,1,1)-> 51]
Scheduling 18 (66) in psp_pss_not_empty, checking s 3 (51): succ st = 1; late_start = 22; latency = 1
Processing edge: [66 -(T,1,1)-> 55]
Scheduling 18 (66) in psp_pss_not_empty, checking s 7 (55): succ st = 21; late_start = 22; latency = 1
Processing edge: [66 -(T,1,1)-> 59]
Scheduling 18 (66) in psp_pss_not_empty, checking s 11 (59): succ st = 19; late_start = 22; latency = 1
Processing edge: [66 -(T,1,1)-> 63]
Scheduling 18 (66) in psp_pss_not_empty, checking s 15 (63): succ st = 18; late_start = 22; latency = 1
Processing edge: [66 -(T,1,1)-> 66]
Scheduling 18 (66) in psp_pss_not_empty, checking s 18 (66): the node is not scheduled
Trying to schedule node 18 INSN = 66 in (22 .. 20) step -1
must_precede: 7
must_follow:
Scheduled w/o split in 22
Processing edge: [51 -(A,0,1)-> 50]
Scheduling 2 (50) in psp_pss_not_empty, checking p 3 (51): pred st = 1; early_start = -21; latency = 0
Processing edge: [48 -(T,2,0)-> 50]
Scheduling 2 (50) in psp_pss_not_empty, checking p 0 (48): the node is not scheduled
Processing edge: [49 -(T,2,0)-> 50]
Scheduling 2 (50) in psp_pss_not_empty, checking p 1 (49): the node is not scheduled
Processing edge: [50 -(A,0,1)-> 49]
Scheduling 2 (50) in psp_pss_not_empty, checking s 1 (49): the node is not scheduled
Processing edge: [50 -(A,0,1)-> 48]
Scheduling 2 (50) in psp_pss_not_empty, checking s 0 (48): the node is not scheduled
Processing edge: [50 -(T,4,0)-> 51]
Scheduling 2 (50) in psp_pss_not_empty, checking s 3 (51): succ st = 1; late_start = -3; latency = 4
Trying to schedule node 2 INSN = 50 in (-3 .. -22) step -1
must_precede: 3
must_follow:
Scheduled w/o split in -5
Processing edge: [55 -(A,0,1)-> 54]
Scheduling 6 (54) in psp_pss_not_empty, checking p 7 (55): pred st = 21; early_start = -1; latency = 0
Processing edge: [52 -(T,2,0)-> 54]
Scheduling 6 (54) in psp_pss_not_empty, checking p 4 (52): the node is not scheduled
Processing edge: [53 -(T,2,0)-> 54]
Scheduling 6 (54) in psp_pss_not_empty, checking p 5 (53): the node is not scheduled
Processing edge: [54 -(A,0,1)-> 53]
Scheduling 6 (54) in psp_pss_not_empty, checking s 5 (53): the node is not scheduled
Processing edge: [54 -(A,0,1)-> 52]
Scheduling 6 (54) in psp_pss_not_empty, checking s 4 (52): the node is not scheduled
Processing edge: [54 -(T,4,0)-> 55]
Scheduling 6 (54) in psp_pss_not_empty, checking s 7 (55): succ st = 21; late_start = 17; latency = 4
Trying to schedule node 6 INSN = 54 in (17 .. -2) step -1
must_precede: 7
must_follow:
Scheduled w/o split in 16
Processing edge: [59 -(A,0,1)-> 58]
Scheduling 10 (58) in psp_pss_not_empty, checking p 11 (59): pred st = 19; early_start = -3; latency = 0
Processing edge: [56 -(T,2,0)-> 58]
Scheduling 10 (58) in psp_pss_not_empty, checking p 8 (56): the node is not scheduled
Processing edge: [57 -(T,2,0)-> 58]
Scheduling 10 (58) in psp_pss_not_empty, checking p 9 (57): the node is not scheduled
Processing edge: [58 -(A,0,1)-> 57]
Scheduling 10 (58) in psp_pss_not_empty, checking s 9 (57): the node is not scheduled
Processing edge: [58 -(A,0,1)-> 56]
Scheduling 10 (58) in psp_pss_not_empty, checking s 8 (56): the node is not scheduled
Processing edge: [58 -(T,4,0)-> 59]
Scheduling 10 (58) in psp_pss_not_empty, checking s 11 (59): succ st = 19; late_start = 15; latency = 4
Trying to schedule node 10 INSN = 58 in (15 .. -4) step -1
must_precede: 11
must_follow:
Scheduled w/o split in 15
Processing edge: [63 -(A,0,1)-> 62]
Scheduling 14 (62) in psp_pss_not_empty, checking p 15 (63): pred st = 18; early_start = -4; latency = 0
Processing edge: [60 -(T,2,0)-> 62]
Scheduling 14 (62) in psp_pss_not_empty, checking p 12 (60): the node is not scheduled
Processing edge: [61 -(T,2,0)-> 62]
Scheduling 14 (62) in psp_pss_not_empty, checking p 13 (61): the node is not scheduled
Processing edge: [62 -(A,0,1)-> 61]
Scheduling 14 (62) in psp_pss_not_empty, checking s 13 (61): the node is not scheduled
Processing edge: [62 -(A,0,1)-> 60]
Scheduling 14 (62) in psp_pss_not_empty, checking s 12 (60): the node is not scheduled
Processing edge: [62 -(T,4,0)-> 63]
Scheduling 14 (62) in psp_pss_not_empty, checking s 15 (63): succ st = 18; late_start = 14; latency = 4
Trying to schedule node 14 INSN = 62 in (14 .. -5) step -1
must_precede: 15
must_follow:
Scheduled w/o split in 14
Processing edge: [50 -(A,0,1)-> 48]
Scheduling 0 (48) in psp_pss_not_empty, checking p 2 (50): pred st = -5; early_start = -27; latency = 0
Processing edge: [65 -(T,1,1)-> 48]
Scheduling 0 (48) in psp_pss_not_empty, checking p 17 (65): the node is not scheduled
Processing edge: [48 -(A,0,0)-> 65]
Scheduling 0 (48) in psp_pss_not_empty, checking s 17 (65): the node is not scheduled
Processing edge: [48 -(T,2,0)-> 50]
Scheduling 0 (48) in psp_pss_not_empty, checking s 2 (50): succ st = -5; late_start = -7; latency = 2
Trying to schedule node 0 INSN = 48 in (-7 .. -28) step -1
must_precede: 2
must_follow:
Scheduled w/o split in -9
Processing edge: [50 -(A,0,1)-> 49]
Scheduling 1 (49) in psp_pss_not_empty, checking p 2 (50): pred st = -5; early_start = -27; latency = 0
Processing edge: [64 -(T,1,1)-> 49]
Scheduling 1 (49) in psp_pss_not_empty, checking p 16 (64): the node is not scheduled
Processing edge: [49 -(A,0,0)-> 64]
Scheduling 1 (49) in psp_pss_not_empty, checking s 16 (64): the node is not scheduled
Processing edge: [49 -(T,2,0)-> 50]
Scheduling 1 (49) in psp_pss_not_empty, checking s 2 (50): succ st = -5; late_start = -7; latency = 2
Trying to schedule node 1 INSN = 49 in (-7 .. -28) step -1
must_precede: 2
must_follow:
Scheduled w/o split in -10
Processing edge: [54 -(A,0,1)-> 52]
Scheduling 4 (52) in psp_pss_not_empty, checking p 6 (54): pred st = 16; early_start = -6; latency = 0
Processing edge: [65 -(T,1,1)-> 52]
Scheduling 4 (52) in psp_pss_not_empty, checking p 17 (65): the node is not scheduled
Processing edge: [52 -(A,0,0)-> 65]
Scheduling 4 (52) in psp_pss_not_empty, checking s 17 (65): the node is not scheduled
Processing edge: [52 -(T,2,0)-> 54]
Scheduling 4 (52) in psp_pss_not_empty, checking s 6 (54): succ st = 16; late_start = 14; latency = 2
Trying to schedule node 4 INSN = 52 in (14 .. -7) step -1
must_precede: 6
must_follow:
Scheduled w/o split in 11
Processing edge: [54 -(A,0,1)-> 53]
Scheduling 5 (53) in psp_pss_not_empty, checking p 6 (54): pred st = 16; early_start = -6; latency = 0
Processing edge: [64 -(T,1,1)-> 53]
Scheduling 5 (53) in psp_pss_not_empty, checking p 16 (64): the node is not scheduled
Processing edge: [53 -(A,0,0)-> 64]
Scheduling 5 (53) in psp_pss_not_empty, checking s 16 (64): the node is not scheduled
Processing edge: [53 -(T,2,0)-> 54]
Scheduling 5 (53) in psp_pss_not_empty, checking s 6 (54): succ st = 16; late_start = 14; latency = 2
Trying to schedule node 5 INSN = 53 in (14 .. -7) step -1
must_precede: 6
must_follow:
Scheduled w/o split in 10
Processing edge: [58 -(A,0,1)-> 56]
Scheduling 8 (56) in psp_pss_not_empty, checking p 10 (58): pred st = 15; early_start = -7; latency = 0
Processing edge: [65 -(T,1,1)-> 56]
Scheduling 8 (56) in psp_pss_not_empty, checking p 17 (65): the node is not scheduled
Processing edge: [56 -(A,0,0)-> 65]
Scheduling 8 (56) in psp_pss_not_empty, checking s 17 (65): the node is not scheduled
Processing edge: [56 -(T,2,0)-> 58]
Scheduling 8 (56) in psp_pss_not_empty, checking s 10 (58): succ st = 15; late_start = 13; latency = 2
Trying to schedule node 8 INSN = 56 in (13 .. -8) step -1
must_precede: 10
must_follow:
Scheduled w/o split in 9
Processing edge: [58 -(A,0,1)-> 57]
Scheduling 9 (57) in psp_pss_not_empty, checking p 10 (58): pred st = 15; early_start = -7; latency = 0
Processing edge: [64 -(T,1,1)-> 57]
Scheduling 9 (57) in psp_pss_not_empty, checking p 16 (64): the node is not scheduled
Processing edge: [57 -(A,0,0)-> 64]
Scheduling 9 (57) in psp_pss_not_empty, checking s 16 (64): the node is not scheduled
Processing edge: [57 -(T,2,0)-> 58]
Scheduling 9 (57) in psp_pss_not_empty, checking s 10 (58): succ st = 15; late_start = 13; latency = 2
Trying to schedule node 9 INSN = 57 in (13 .. -8) step -1
must_precede: 10
must_follow:
Scheduled w/o split in 8
Processing edge: [62 -(A,0,1)-> 60]
Scheduling 12 (60) in psp_pss_not_empty, checking p 14 (62): pred st = 14; early_start = -8; latency = 0
Processing edge: [65 -(T,1,1)-> 60]
Scheduling 12 (60) in psp_pss_not_empty, checking p 17 (65): the node is not scheduled
Processing edge: [60 -(A,0,0)-> 65]
Scheduling 12 (60) in psp_pss_not_empty, checking s 17 (65): the node is not scheduled
Processing edge: [60 -(T,2,0)-> 62]
Scheduling 12 (60) in psp_pss_not_empty, checking s 14 (62): succ st = 14; late_start = 12; latency = 2
Trying to schedule node 12 INSN = 60 in (12 .. -9) step -1
must_precede: 14
must_follow:
Scheduled w/o split in 7
Processing edge: [62 -(A,0,1)-> 61]
Scheduling 13 (61) in psp_pss_not_empty, checking p 14 (62): pred st = 14; early_start = -8; latency = 0
Processing edge: [64 -(T,1,1)-> 61]
Scheduling 13 (61) in psp_pss_not_empty, checking p 16 (64): the node is not scheduled
Processing edge: [61 -(A,0,0)-> 64]
Scheduling 13 (61) in psp_pss_not_empty, checking s 16 (64): the node is not scheduled
Processing edge: [61 -(T,2,0)-> 62]
Scheduling 13 (61) in psp_pss_not_empty, checking s 14 (62): succ st = 14; late_start = 12; latency = 2
Trying to schedule node 13 INSN = 61 in (12 .. -9) step -1
must_precede: 14
must_follow:
Scheduled w/o split in 6
Processing edge: [64 -(T,1,1)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 16 (64): the node is not scheduled
Processing edge: [61 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 13 (61): pred st = 6; early_start = 6; latency = 0
Processing edge: [57 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 9 (57): pred st = 8; early_start = 8; latency = 0
Processing edge: [53 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 5 (53): pred st = 10; early_start = 10; latency = 0
Processing edge: [49 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 1 (49): pred st = -10; early_start = 10; latency = 0
Processing edge: [64 -(T,1,1)-> 49]
Scheduling 16 (64) in psp_pss_not_empty, checking s 1 (49): succ st = -10; late_start = 11; latency = 1
Processing edge: [64 -(T,1,1)-> 53]
Scheduling 16 (64) in psp_pss_not_empty, checking s 5 (53): succ st = 10; late_start = 11; latency = 1
Processing edge: [64 -(T,1,1)-> 57]
Scheduling 16 (64) in psp_pss_not_empty, checking s 9 (57): succ st = 8; late_start = 11; latency = 1
Processing edge: [64 -(T,1,1)-> 61]
Scheduling 16 (64) in psp_pss_not_empty, checking s 13 (61): succ st = 6; late_start = 11; latency = 1
Processing edge: [64 -(T,1,1)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking s 16 (64): the node is not scheduled
Trying to schedule node 16 INSN = 64 in (11 .. 9) step -1
must_precede: 5
must_follow:
split_row=0
crr_insn->node=18, crr_insn->cycle=22, min_cycle=-10
crr_insn->node=3, crr_insn->cycle=1, min_cycle=-10
crr_insn->node=13, crr_insn->cycle=6, min_cycle=-10
crr_insn->node=12, crr_insn->cycle=7, min_cycle=-10
crr_insn->node=9, crr_insn->cycle=8, min_cycle=-10
crr_insn->node=8, crr_insn->cycle=9, min_cycle=-10
crr_insn->node=5, crr_insn->cycle=10, min_cycle=-10
crr_insn->node=4, crr_insn->cycle=11, min_cycle=-10
crr_insn->node=1, crr_insn->cycle=-10, min_cycle=-10
crr_insn->node=0, crr_insn->cycle=-9, min_cycle=-10
crr_insn->node=14, crr_insn->cycle=14, min_cycle=-10
crr_insn->node=10, crr_insn->cycle=15, min_cycle=-10
crr_insn->node=6, crr_insn->cycle=16, min_cycle=-10
crr_insn->node=2, crr_insn->cycle=-5, min_cycle=-10
crr_insn->node=15, crr_insn->cycle=18, min_cycle=-10
crr_insn->node=11, crr_insn->cycle=19, min_cycle=-10
crr_insn->node=7, crr_insn->cycle=21, min_cycle=-10
min_cycle=1, max_cycle=34
num_splits=1
Processing edge: [64 -(T,1,1)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 16 (64): the node is not scheduled
Processing edge: [61 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 13 (61): pred st = 17; early_start = 17; latency = 0
Processing edge: [57 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 9 (57): pred st = 19; early_start = 19; latency = 0
Processing edge: [53 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 5 (53): pred st = 21; early_start = 21; latency = 0
Processing edge: [49 -(A,0,0)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking p 1 (49): pred st = 1; early_start = 21; latency = 0
Processing edge: [64 -(T,1,1)-> 49]
Scheduling 16 (64) in psp_pss_not_empty, checking s 1 (49): succ st = 1; late_start = 23; latency = 1
Processing edge: [64 -(T,1,1)-> 53]
Scheduling 16 (64) in psp_pss_not_empty, checking s 5 (53): succ st = 21; late_start = 23; latency = 1
Processing edge: [64 -(T,1,1)-> 57]
Scheduling 16 (64) in psp_pss_not_empty, checking s 9 (57): succ st = 19; late_start = 23; latency = 1
Processing edge: [64 -(T,1,1)-> 61]
Scheduling 16 (64) in psp_pss_not_empty, checking s 13 (61): succ st = 17; late_start = 23; latency = 1
Processing edge: [64 -(T,1,1)-> 64]
Scheduling 16 (64) in psp_pss_not_empty, checking s 16 (64): the node is not scheduled
Trying to schedule node 16 INSN = 64 in (23 .. 20) step -1
must_precede: 5
must_follow:
Scheduled w/o split in 23
Processing edge: [65 -(T,1,1)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 17 (65): the node is not scheduled
Processing edge: [60 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 12 (60): pred st = 18; early_start = 18; latency = 0
Processing edge: [56 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 8 (56): pred st = 20; early_start = 20; latency = 0
Processing edge: [52 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 4 (52): pred st = 22; early_start = 22; latency = 0
Processing edge: [48 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 0 (48): pred st = 2; early_start = 22; latency = 0
Processing edge: [65 -(T,1,1)-> 48]
Scheduling 17 (65) in psp_pss_not_empty, checking s 0 (48): succ st = 2; late_start = 24; latency = 1
Processing edge: [65 -(T,1,1)-> 52]
Scheduling 17 (65) in psp_pss_not_empty, checking s 4 (52): succ st = 22; late_start = 24; latency = 1
Processing edge: [65 -(T,1,1)-> 56]
Scheduling 17 (65) in psp_pss_not_empty, checking s 8 (56): succ st = 20; late_start = 24; latency = 1
Processing edge: [65 -(T,1,1)-> 60]
Scheduling 17 (65) in psp_pss_not_empty, checking s 12 (60): succ st = 18; late_start = 24; latency = 1
Processing edge: [65 -(T,1,1)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking s 17 (65): the node is not scheduled
Trying to schedule node 17 INSN = 65 in (24 .. 21) step -1
must_precede: 4
must_follow:
split_row=1
crr_insn->node=16, crr_insn->cycle=23, min_cycle=1
crr_insn->node=1, crr_insn->cycle=1, min_cycle=1
crr_insn->node=0, crr_insn->cycle=2, min_cycle=1
crr_insn->node=14, crr_insn->cycle=26, min_cycle=1
crr_insn->node=10, crr_insn->cycle=27, min_cycle=1
crr_insn->node=6, crr_insn->cycle=28, min_cycle=1
crr_insn->node=2, crr_insn->cycle=6, min_cycle=1
crr_insn->node=15, crr_insn->cycle=30, min_cycle=1
crr_insn->node=11, crr_insn->cycle=31, min_cycle=1
crr_insn->node=7, crr_insn->cycle=33, min_cycle=1
crr_insn->node=18, crr_insn->cycle=34, min_cycle=1
crr_insn->node=3, crr_insn->cycle=12, min_cycle=1
crr_insn->node=13, crr_insn->cycle=17, min_cycle=1
crr_insn->node=12, crr_insn->cycle=18, min_cycle=1
crr_insn->node=9, crr_insn->cycle=19, min_cycle=1
crr_insn->node=8, crr_insn->cycle=20, min_cycle=1
crr_insn->node=5, crr_insn->cycle=21, min_cycle=1
crr_insn->node=4, crr_insn->cycle=22, min_cycle=1
min_cycle=0, max_cycle=35
num_splits=1
Processing edge: [65 -(T,1,1)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 17 (65): the node is not scheduled
Processing edge: [60 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 12 (60): pred st = 18; early_start = 18; latency = 0
Processing edge: [56 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 8 (56): pred st = 20; early_start = 20; latency = 0
Processing edge: [52 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 4 (52): pred st = 22; early_start = 22; latency = 0
Processing edge: [48 -(A,0,0)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking p 0 (48): pred st = 2; early_start = 22; latency = 0
Processing edge: [65 -(T,1,1)-> 48]
Scheduling 17 (65) in psp_pss_not_empty, checking s 0 (48): succ st = 2; late_start = 25; latency = 1
Processing edge: [65 -(T,1,1)-> 52]
Scheduling 17 (65) in psp_pss_not_empty, checking s 4 (52): succ st = 22; late_start = 25; latency = 1
Processing edge: [65 -(T,1,1)-> 56]
Scheduling 17 (65) in psp_pss_not_empty, checking s 8 (56): succ st = 20; late_start = 25; latency = 1
Processing edge: [65 -(T,1,1)-> 60]
Scheduling 17 (65) in psp_pss_not_empty, checking s 12 (60): succ st = 18; late_start = 25; latency = 1
Processing edge: [65 -(T,1,1)-> 65]
Scheduling 17 (65) in psp_pss_not_empty, checking s 17 (65): the node is not scheduled
Trying to schedule node 17 INSN = 65 in (25 .. 21) step -1
must_precede: 4
must_follow:
Scheduled w/o split in 25
SMS succeeded 24 2 (with ii, sc)
[ROW 0 ]: 49,
[ROW 1 ]: 65,
[ROW 2 ]: 48,
[ROW 3 ]: 62,
[ROW 4 ]: 58,
[ROW 5 ]: 54,
[ROW 6 ]: 50,
[ROW 7 ]: 63,
[ROW 8 ]: 59,
[ROW 9 ]:
[ROW 10 ]: 55,
[ROW 11 ]: 66,
[ROW 12 ]: 51,
[ROW 13 ]:
[ROW 14 ]:
[ROW 15 ]:
[ROW 16 ]:
[ROW 17 ]: 61,
[ROW 18 ]: 60,
[ROW 19 ]: 57,
[ROW 20 ]: 56,
[ROW 21 ]: 53,
[ROW 22 ]: 52,
[ROW 23 ]: 64, SMS Branch (19) will later be scheduled at cycle -1.
crr_insn->node=1, crr_insn->cycle=0, min_cycle=0
crr_insn->node=17, crr_insn->cycle=25, min_cycle=0
crr_insn->node=0, crr_insn->cycle=2, min_cycle=0
crr_insn->node=14, crr_insn->cycle=27, min_cycle=0
crr_insn->node=10, crr_insn->cycle=28, min_cycle=0
crr_insn->node=6, crr_insn->cycle=29, min_cycle=0
crr_insn->node=2, crr_insn->cycle=6, min_cycle=0
crr_insn->node=15, crr_insn->cycle=31, min_cycle=0
crr_insn->node=11, crr_insn->cycle=32, min_cycle=0
crr_insn->node=7, crr_insn->cycle=34, min_cycle=0
crr_insn->node=18, crr_insn->cycle=35, min_cycle=0
crr_insn->node=3, crr_insn->cycle=12, min_cycle=0
crr_insn->node=13, crr_insn->cycle=17, min_cycle=0
crr_insn->node=12, crr_insn->cycle=18, min_cycle=0
crr_insn->node=9, crr_insn->cycle=19, min_cycle=0
crr_insn->node=8, crr_insn->cycle=20, min_cycle=0
crr_insn->node=5, crr_insn->cycle=21, min_cycle=0
crr_insn->node=4, crr_insn->cycle=22, min_cycle=0
crr_insn->node=16, crr_insn->cycle=23, min_cycle=0
changing bb of uid 89
unscanned insn
verify found no changes in insn with uid = 85.
Edge 3->3 redirected to 5
Node = 0; INSN = 48
asap = 0:
time = 2:
nreg_moves = 0:
Node = 1; INSN = 49
asap = 0:
time = 0:
nreg_moves = 0:
Node = 2; INSN = 50
asap = 2:
time = 6:
nreg_moves = 0:
Node = 3; INSN = 51
asap = 6:
time = 12:
nreg_moves = 0:
Node = 4; INSN = 52
asap = 0:
time = 22:
nreg_moves = 0:
Node = 5; INSN = 53
asap = 0:
time = 21:
nreg_moves = 0:
Node = 6; INSN = 54
asap = 2:
time = 29:
nreg_moves = 0:
Node = 7; INSN = 55
asap = 6:
time = 34:
nreg_moves = 0:
Node = 8; INSN = 56
asap = 0:
time = 20:
nreg_moves = 0:
Node = 9; INSN = 57
asap = 0:
time = 19:
nreg_moves = 0:
Node = 10; INSN = 58
asap = 2:
time = 28:
nreg_moves = 0:
Node = 11; INSN = 59
asap = 6:
time = 32:
nreg_moves = 0:
Node = 12; INSN = 60
asap = 0:
time = 18:
nreg_moves = 0:
Node = 13; INSN = 61
asap = 0:
time = 17:
nreg_moves = 0:
Node = 14; INSN = 62
asap = 2:
time = 27:
nreg_moves = 0:
Node = 15; INSN = 63
asap = 6:
time = 31:
nreg_moves = 0:
Node = 16; INSN = 64
asap = 0:
time = 23:
nreg_moves = 0:
Node = 17; INSN = 65
asap = 0:
time = 25:
nreg_moves = 0:
Node = 18; INSN = 66
asap = 6:
time = 35:
nreg_moves = 0:
Node = 19; INSN = 85
asap = 6:
time = 0:
nreg_moves = 0:
deleting insn with uid = 91.
deleting insn with uid = 93.
deleting insn with uid = 95.
deleting insn with uid = 97.
deleting insn with uid = 99.
deleting insn with uid = 101.
deleting insn with uid = 103.
deleting insn with uid = 105.
deleting insn with uid = 107.
deleting insn with uid = 109.
deleting insn with uid = 111.
changing bb of uid 113
unscanned insn
Fallthru edge 2->6 redirected to 6
scanning new insn with uid = 92.
scanning new insn with uid = 94.
scanning new insn with uid = 96.
scanning new insn with uid = 98.
scanning new insn with uid = 100.
scanning new insn with uid = 102.
scanning new insn with uid = 104.
scanning new insn with uid = 106.
scanning new insn with uid = 108.
scanning new insn with uid = 110.
scanning new insn with uid = 112.
deleting insn with uid = 114.
deleting insn with uid = 116.
deleting insn with uid = 118.
deleting insn with uid = 120.
deleting insn with uid = 122.
deleting insn with uid = 124.
deleting insn with uid = 126.
deleting insn with uid = 128.
changing bb of uid 130
unscanned insn
Fallthru edge 3->7 redirected to 7
scanning new insn with uid = 115.
scanning new insn with uid = 117.
scanning new insn with uid = 119.
scanning new insn with uid = 121.
scanning new insn with uid = 123.
scanning new insn with uid = 125.
scanning new insn with uid = 127.
scanning new insn with uid = 129.
scanning new insn with uid = 132.
scanning new insn with uid = 134.
Reordered sequence:
2 bb 2 [385]
3 bb 6 [385]
4 bb 3 [9615]
5 bb 7 [385]
6 bb 5 [9230]
7 bb 4 [385]
foo
Dataflow summary:
;; invalidated by call 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave]
;; hardware regs used 1 [1] 67 [ap] 113 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 65 [lr] 67 [ap] 113 [sfp]
;; exit block uses 1 [1] 31 [31] 113 [sfp]
;; regs ever live 3[3] 4[4] 5[5]
;; ref usage r1={1d,7u} r3={1d,1u} r4={1d,1u} r5={1d,1u} r6={1d} r7={1d} r8={1d} r9={1d} r10={1d} r11={1d} r31={1d,7u} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r65={1d} r67={1d,6u} r113={1d,7u} r155={3d,10u} r156={3d,10u} r157={3d,10u} r161={2d,2u} r162={2d,2u} r163={2d,2u} r164={2d,2u} r165={2d,2u} r166={2d,2u} r167={2d,2u} r168={2d,2u} r169={2d,2u} r170={2d,2u} r171={2d,2u} r172={2d,2u} r174={2d,2u}
;; total ref usage 143{57d,86u,0e} in 45{45 regular + 0 call} insns.
;; Reaching defs:
sparse invalidated
dense invalidated 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
1[0,1] 3[1,1] 4[2,1] 5[3,1] 6[4,1] 7[5,1] 8[6,1] 9[7,1] 10[8,1] 11[9,1] 31[10,1] 33[11,1] 34[12,1] 35[13,1] 36[14,1] 37[15,1] 38[16,1] 39[17,1] 40[18,1] 65[19,1] 67[20,1] 113[21,1] 155[22,2] 156[24,2] 157[26,2] 161[28,1] 162[29,1] 163[30,1] 164[31,1] 165[32,1] 166[33,1] 167[34,1] 168[35,1] 169[36,1] 170[37,1] 171[38,1] 172[39,1] 174[40,2]
(note:HI 36 0 41 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ d0(bb 0 insn -1) }u1(31){ d10(bb 0 insn -1) }u2(67){ d20(bb 0 insn -1) }u3(113){ d21(bb 0 insn -1) }}
;; lr in 1 [1] 3 [3] 4 [4] 5 [5] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 3 [3] 4 [4] 5 [5] 31 [31] 67 [ap] 113 [sfp]
;; lr def 155 156 157 174
;; live in 1 [1] 3 [3] 4 [4] 5 [5] 31 [31] 67 [ap] 113 [sfp]
;; live gen 155 156 157 174
;; live kill
;; rd in (22)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21
;; rd gen (4)
22, 24, 26, 40
;; rd kill (8)
22, 23, 24, 25, 26, 27, 40, 41
;; DU chains for insn luid 0 uid 44
;; reg 155 { u40(bb 4 insn 66) u36(bb 4 insn 63) u30(bb 4 insn 59) u24(bb 4 insn 55) u18(bb 4 insn 51) }
;; DU chains for insn luid 1 uid 45
;; reg 156 { u39(bb 4 insn 65) u32(bb 4 insn 60) u26(bb 4 insn 56) u20(bb 4 insn 52) u14(bb 4 insn 48) }
;; DU chains for insn luid 2 uid 46
;; reg 157 { u38(bb 4 insn 64) u33(bb 4 insn 61) u27(bb 4 insn 57) u21(bb 4 insn 53) u15(bb 4 insn 49) }
;; DU chains for insn luid 3 uid 86
;; reg 174 { u42(bb 4 insn 85) u41(bb 4 insn 85) }
;; Pred edge ENTRY [100.0%] (fallthru)
(note:HI 41 36 37 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note:HI 37 41 38 2 NOTE_INSN_DELETED)
(note:HI 38 37 39 2 NOTE_INSN_DELETED)
(note:HI 39 38 40 2 NOTE_INSN_DELETED)
(note:HI 40 39 44 2 NOTE_INSN_FUNCTION_BEG)
(insn:HI 44 40 45 2 sms-6.c:6 (set (reg/f:SI 155 [ ivtmp.43 ])
(reg:SI 3 3 [ a ])) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 3 3 [ a ])
(nil)))
(insn:HI 45 44 46 2 sms-6.c:6 (set (reg/f:SI 156 [ ivtmp.42 ])
(reg:SI 5 5 [ c ])) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 5 5 [ c ])
(nil)))
(insn:HI 46 45 86 2 sms-6.c:6 (set (reg/f:SI 157 [ ivtmp.40 ])
(reg:SI 4 4 [ b ])) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 4 4 [ b ])
(nil)))
(insn:HI 86 46 113 2 sms-6.c:6 (set (reg:SI 174)
(const_int 24 [0x18])) 334 {*movsi_internal1} (nil))
;; End of basic block 2 -> ( 3)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; rd out (26)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 24, 26, 40
;; UD chains for artificial uses
;; reg 1 { d0(bb 0 insn -1) }
;; reg 31 { d10(bb 0 insn -1) }
;; reg 67 { d20(bb 0 insn -1) }
;; reg 113 { d21(bb 0 insn -1) }
;; UD chains for insn luid 0 uid 44
;; reg 3 { d1(bb 0 insn -1) }
;; UD chains for insn luid 1 uid 45
;; reg 5 { d3(bb 0 insn -1) }
;; UD chains for insn luid 2 uid 46
;; reg 4 { d2(bb 0 insn -1) }
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; DU chains for insn luid 0 uid 92
;; reg 162 { }
;; DU chains for insn luid 0 uid 94
;; reg 161 { }
;; DU chains for insn luid 0 uid 96
;; reg 163 { }
;; DU chains for insn luid 0 uid 100
;; reg 171 { }
;; DU chains for insn luid 0 uid 102
;; reg 170 { }
;; DU chains for insn luid 0 uid 104
;; reg 168 { }
;; DU chains for insn luid 0 uid 106
;; reg 167 { }
;; DU chains for insn luid 0 uid 108
;; reg 165 { }
;; DU chains for insn luid 0 uid 110
;; reg 164 { }
;; DU chains for insn luid 0 uid 112
;; reg 157 { }
;; Pred edge 2 [100.0%] (fallthru)
(note 113 86 92 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 92 113 94 3 sms-6.c:11 (set (reg:SI 162)
(mem:SI (reg/f:SI 157 [ ivtmp.40 ]) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 94 92 96 3 sms-6.c:11 (set (reg:SI 161)
(mem:SI (reg/f:SI 156 [ ivtmp.42 ]) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 96 94 98 3 sms-6.c:11 (set (reg:SI 163)
(mult:SI (reg:SI 161)
(reg:SI 162))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 161)
(expr_list:REG_DEAD (reg:SI 162)
(nil))))
(insn 98 96 100 3 sms-6.c:11 (set (mem:SI (reg/f:SI 155 [ ivtmp.43 ]) [3 S4 A32])
(reg:SI 163)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 163)
(nil)))
(insn 100 98 102 3 sms-6.c:14 (set (reg:SI 171)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 12 [0xc])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 102 100 104 3 sms-6.c:14 (set (reg:SI 170)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 12 [0xc])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 104 102 106 3 sms-6.c:13 (set (reg:SI 168)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 8 [0x8])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 106 104 108 3 sms-6.c:13 (set (reg:SI 167)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 8 [0x8])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 108 106 110 3 sms-6.c:12 (set (reg:SI 165)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 4 [0x4])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 110 108 112 3 sms-6.c:12 (set (reg:SI 164)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 4 [0x4])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn 112 110 67 3 sms-6.c:14 (set (reg/f:SI 157 [ ivtmp.40 ])
(plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
;; End of basic block 3 -> ( 4)
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
;; UD chains for insn luid 0 uid 92
;; reg 157 { }
;; UD chains for insn luid 0 uid 94
;; reg 156 { }
;; UD chains for insn luid 0 uid 96
;; reg 161 { }
;; reg 162 { }
;; UD chains for insn luid 0 uid 98
;; reg 155 { }
;; reg 163 { }
;; UD chains for insn luid 0 uid 100
;; reg 157 { }
;; UD chains for insn luid 0 uid 102
;; reg 156 { }
;; UD chains for insn luid 0 uid 104
;; reg 157 { }
;; UD chains for insn luid 0 uid 106
;; reg 156 { }
;; UD chains for insn luid 0 uid 108
;; reg 157 { }
;; UD chains for insn luid 0 uid 110
;; reg 156 { }
;; UD chains for insn luid 0 uid 112
;; reg 157 { }
;; Succ edge 4 [100.0%] (fallthru)
;; Start of basic block ( 3 6) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u10(1){ d0(bb 0 insn -1) }u11(31){ d10(bb 0 insn -1) }u12(67){ d20(bb 0 insn -1) }u13(113){ d21(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; lr def 155 156 157 161 162 163 164 165 166 167 168 169 170 171 172 174
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; live gen 155 156 157 161 162 163 164 165 166 167 168 169 170 171 172 174
;; live kill
;; rd in (42)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41
;; rd gen (16)
23, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41
;; rd kill (20)
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41
;; DU chains for insn luid 1 uid 49
;; reg 162 { u17(bb 4 insn 50) }
;; DU chains for insn luid 17 uid 65
;; reg 156 { u39(bb 4 insn 65) u32(bb 4 insn 60) u26(bb 4 insn 56) u20(bb 4 insn 52) u14(bb 4 insn 48) }
;; DU chains for insn luid 0 uid 48
;; reg 161 { u16(bb 4 insn 50) }
;; DU chains for insn luid 14 uid 62
;; reg 172 { u37(bb 4 insn 63) }
;; DU chains for insn luid 10 uid 58
;; reg 169 { u31(bb 4 insn 59) }
;; DU chains for insn luid 6 uid 54
;; reg 166 { u25(bb 4 insn 55) }
;; DU chains for insn luid 2 uid 50
;; reg 163 { u19(bb 4 insn 51) }
;; DU chains for insn luid 18 uid 66
;; reg 155 { u40(bb 4 insn 66) u36(bb 4 insn 63) u30(bb 4 insn 59) u24(bb 4 insn 55) u18(bb 4 insn 51) }
;; DU chains for insn luid 13 uid 61
;; reg 171 { u35(bb 4 insn 62) }
;; DU chains for insn luid 12 uid 60
;; reg 170 { u34(bb 4 insn 62) }
;; DU chains for insn luid 9 uid 57
;; reg 168 { u29(bb 4 insn 58) }
;; DU chains for insn luid 8 uid 56
;; reg 167 { u28(bb 4 insn 58) }
;; DU chains for insn luid 5 uid 53
;; reg 165 { u23(bb 4 insn 54) }
;; DU chains for insn luid 4 uid 52
;; reg 164 { u22(bb 4 insn 54) }
;; DU chains for insn luid 16 uid 64
;; reg 157 { u38(bb 4 insn 64) u33(bb 4 insn 61) u27(bb 4 insn 57) u21(bb 4 insn 53) u15(bb 4 insn 49) }
;; DU chains for insn luid 19 uid 85
;; reg 174 { u42(bb 4 insn 85) u41(bb 4 insn 85) }
;; Pred edge 3 [100.0%] (fallthru)
;; Pred edge 6 [100.0%]
(code_label:HI 67 112 47 4 2 "" [1 uses])
(note:HI 47 67 49 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn:HI 49 47 65 4 sms-6.c:11 (set (reg:SI 162)
(mem:SI (reg/f:SI 157 [ ivtmp.40 ]) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 65 49 48 4 sms-6.c:14 (set (reg/f:SI 156 [ ivtmp.42 ])
(plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
(insn:HI 48 65 62 4 sms-6.c:11 (set (reg:SI 161)
(mem:SI (reg/f:SI 156 [ ivtmp.42 ]) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 62 48 58 4 sms-6.c:14 (set (reg:SI 172)
(mult:SI (reg:SI 170)
(reg:SI 171))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 171)
(expr_list:REG_DEAD (reg:SI 170)
(nil))))
(insn:HI 58 62 54 4 sms-6.c:13 (set (reg:SI 169)
(mult:SI (reg:SI 167)
(reg:SI 168))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 168)
(expr_list:REG_DEAD (reg:SI 167)
(nil))))
(insn:HI 54 58 50 4 sms-6.c:12 (set (reg:SI 166)
(mult:SI (reg:SI 164)
(reg:SI 165))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 165)
(expr_list:REG_DEAD (reg:SI 164)
(nil))))
(insn:HI 50 54 63 4 sms-6.c:11 (set (reg:SI 163)
(mult:SI (reg:SI 161)
(reg:SI 162))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 162)
(expr_list:REG_DEAD (reg:SI 161)
(nil))))
(insn:HI 63 50 59 4 sms-6.c:14 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 172)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 172)
(nil)))
(insn:HI 59 63 55 4 sms-6.c:13 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 169)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 169)
(nil)))
(insn:HI 55 59 66 4 sms-6.c:12 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 166)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 166)
(nil)))
(insn:HI 66 55 51 4 sms-6.c:14 (set (reg/f:SI 155 [ ivtmp.43 ])
(plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
(insn:HI 51 66 61 4 sms-6.c:11 (set (mem:SI (reg/f:SI 155 [ ivtmp.43 ]) [3 S4 A32])
(reg:SI 163)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 163)
(nil)))
(insn:HI 61 51 60 4 sms-6.c:14 (set (reg:SI 171)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 12 [0xc])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 60 61 57 4 sms-6.c:14 (set (reg:SI 170)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 12 [0xc])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 57 60 56 4 sms-6.c:13 (set (reg:SI 168)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 8 [0x8])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 56 57 53 4 sms-6.c:13 (set (reg:SI 167)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 8 [0x8])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 53 56 52 4 sms-6.c:12 (set (reg:SI 165)
(mem:SI (plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 4 [0x4])) [5 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 52 53 64 4 sms-6.c:12 (set (reg:SI 164)
(mem:SI (plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 4 [0x4])) [4 S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 64 52 85 4 sms-6.c:14 (set (reg/f:SI 157 [ ivtmp.40 ])
(plus:SI (reg/f:SI 157 [ ivtmp.40 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
(jump_insn:HI 85 64 130 4 sms-6.c:9 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 174)
(const_int 1 [0x1]))
(label_ref:SI 90)
(pc)))
(set (reg:SI 174)
(plus:SI (reg:SI 174)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9600 [0x2580])
(nil)))
;; End of basic block 4 -> ( 6 5)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 155 156 157 174
;; rd out (38)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41
;; UD chains for artificial uses
;; reg 1 { d0(bb 0 insn -1) }
;; reg 31 { d10(bb 0 insn -1) }
;; reg 67 { d20(bb 0 insn -1) }
;; reg 113 { d21(bb 0 insn -1) }
;; UD chains for insn luid 1 uid 49
;; reg 157 { d27(bb 4 insn 64) d26(bb 2 insn 46) }
;; UD chains for insn luid 17 uid 65
;; reg 156 { d25(bb 4 insn 65) d24(bb 2 insn 45) }
;; UD chains for insn luid 0 uid 48
;; reg 156 { d25(bb 4 insn 65) d24(bb 2 insn 45) }
;; UD chains for insn luid 14 uid 62
;; reg 170 { d37(bb 4 insn 60) }
;; reg 171 { d38(bb 4 insn 61) }
;; UD chains for insn luid 10 uid 58
;; reg 167 { d34(bb 4 insn 56) }
;; reg 168 { d35(bb 4 insn 57) }
;; UD chains for insn luid 6 uid 54
;; reg 164 { d31(bb 4 insn 52) }
;; reg 165 { d32(bb 4 insn 53) }
;; UD chains for insn luid 2 uid 50
;; reg 161 { d28(bb 4 insn 48) }
;; reg 162 { d29(bb 4 insn 49) }
;; UD chains for insn luid 15 uid 63
;; reg 155 { d23(bb 4 insn 66) d22(bb 2 insn 44) }
;; reg 172 { d39(bb 4 insn 62) }
;; UD chains for insn luid 11 uid 59
;; reg 155 { d23(bb 4 insn 66) d22(bb 2 insn 44) }
;; reg 169 { d36(bb 4 insn 58) }
;; UD chains for insn luid 7 uid 55
;; reg 155 { d23(bb 4 insn 66) d22(bb 2 insn 44) }
;; reg 166 { d33(bb 4 insn 54) }
;; UD chains for insn luid 18 uid 66
;; reg 155 { d23(bb 4 insn 66) d22(bb 2 insn 44) }
;; UD chains for insn luid 3 uid 51
;; reg 155 { d23(bb 4 insn 66) d22(bb 2 insn 44) }
;; reg 163 { d30(bb 4 insn 50) }
;; UD chains for insn luid 13 uid 61
;; reg 157 { d27(bb 4 insn 64) d26(bb 2 insn 46) }
;; UD chains for insn luid 12 uid 60
;; reg 156 { d25(bb 4 insn 65) d24(bb 2 insn 45) }
;; UD chains for insn luid 9 uid 57
;; reg 157 { d27(bb 4 insn 64) d26(bb 2 insn 46) }
;; UD chains for insn luid 8 uid 56
;; reg 156 { d25(bb 4 insn 65) d24(bb 2 insn 45) }
;; UD chains for insn luid 5 uid 53
;; reg 157 { d27(bb 4 insn 64) d26(bb 2 insn 46) }
;; UD chains for insn luid 4 uid 52
;; reg 156 { d25(bb 4 insn 65) d24(bb 2 insn 45) }
;; UD chains for insn luid 16 uid 64
;; reg 157 { d27(bb 4 insn 64) d26(bb 2 insn 46) }
;; UD chains for insn luid 19 uid 85
;; reg 174 { d41(bb 4 insn 85) d40(bb 2 insn 86) }
;; reg 174 { d41(bb 4 insn 85) d40(bb 2 insn 86) }
;; Succ edge 6 [96.0%] (dfs_back)
;; Succ edge 5 [4.0%] (fallthru,loop_exit)
;; Start of basic block ( 4) -> 5
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; DU chains for insn luid 0 uid 115
;; reg 156 { }
;; DU chains for insn luid 0 uid 117
;; reg 172 { }
;; DU chains for insn luid 0 uid 119
;; reg 169 { }
;; DU chains for insn luid 0 uid 121
;; reg 166 { }
;; DU chains for insn luid 0 uid 129
;; reg 155 { }
;; Pred edge 4 [4.0%] (fallthru,loop_exit)
(note 130 85 115 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 115 130 117 5 sms-6.c:14 (set (reg/f:SI 156 [ ivtmp.42 ])
(plus:SI (reg/f:SI 156 [ ivtmp.42 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
(insn 117 115 119 5 sms-6.c:14 (set (reg:SI 172)
(mult:SI (reg:SI 170)
(reg:SI 171))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 170)
(expr_list:REG_DEAD (reg:SI 171)
(nil))))
(insn 119 117 121 5 sms-6.c:13 (set (reg:SI 169)
(mult:SI (reg:SI 167)
(reg:SI 168))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 167)
(expr_list:REG_DEAD (reg:SI 168)
(nil))))
(insn 121 119 123 5 sms-6.c:12 (set (reg:SI 166)
(mult:SI (reg:SI 164)
(reg:SI 165))) 117 {mulsi3_no_mq} (expr_list:REG_DEAD (reg:SI 164)
(expr_list:REG_DEAD (reg:SI 165)
(nil))))
(insn 123 121 125 5 sms-6.c:14 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 172)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 172)
(nil)))
(insn 125 123 127 5 sms-6.c:13 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 169)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 169)
(nil)))
(insn 127 125 129 5 sms-6.c:12 (set (mem:SI (plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 166)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI 166)
(nil)))
(insn 129 127 132 5 sms-6.c:14 (set (reg/f:SI 155 [ ivtmp.43 ])
(plus:SI (reg/f:SI 155 [ ivtmp.43 ])
(const_int 16 [0x10]))) 82 {*addsi3_internal1} (nil))
(jump_insn 132 129 133 5 (set (pc)
(label_ref 131)) -1 (nil))
;; End of basic block 5 -> ( 7)
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
;; UD chains for insn luid 0 uid 115
;; reg 156 { }
;; UD chains for insn luid 0 uid 117
;; reg 170 { }
;; reg 171 { }
;; UD chains for insn luid 0 uid 119
;; reg 167 { }
;; reg 168 { }
;; UD chains for insn luid 0 uid 121
;; reg 164 { }
;; reg 165 { }
;; UD chains for insn luid 0 uid 123
;; reg 155 { }
;; reg 172 { }
;; UD chains for insn luid 0 uid 125
;; reg 155 { }
;; reg 169 { }
;; UD chains for insn luid 0 uid 127
;; reg 155 { }
;; reg 166 { }
;; UD chains for insn luid 0 uid 129
;; reg 155 { }
;; Succ edge 7 [100.0%]
(barrier 133 132 90)
;; Start of basic block ( 4) -> 6
;; bb 6 artificial_defs: { }
;; bb 6 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; Pred edge 4 [96.0%] (dfs_back)
(code_label 90 133 89 6 5 "" [1 uses])
(note 89 90 134 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(jump_insn 134 89 135 6 (set (pc)
(label_ref 67)) -1 (nil))
;; End of basic block 6 -> ( 4)
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
;; Succ edge 4 [100.0%]
(barrier 135 134 131)
;; Start of basic block ( 5) -> 7
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u43(1){ d0(bb 0 insn -1) }u44(31){ d10(bb 0 insn -1) }u45(67){ d20(bb 0 insn -1) }u46(113){ d21(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen
;; live kill
;; rd in (38)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41
;; rd gen (0)
;; rd kill (0)
;; Pred edge 5 [100.0%]
(code_label 131 135 77 7 6 "" [1 uses])
(note:HI 77 131 0 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
;; End of basic block 7 -> ( 1)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; rd out (38)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41
;; UD chains for artificial uses
;; reg 1 { d0(bb 0 insn -1) }
;; reg 31 { d10(bb 0 insn -1) }
;; reg 67 { d20(bb 0 insn -1) }
;; reg 113 { d21(bb 0 insn -1) }
;; Succ edge EXIT [100.0%] (fallthru)
starting the processing of deferred insns
ending the processing of deferred insns
;; Function main (main)
try_optimize_cfg iteration 1
;; 3 loops found
;;
;; Loop 0
;; header 0, latch 1
;; depth 0, outer -1
;; nodes: 0 1 2 3 4 5 6 7 8
;;
;; Loop 2
;; header 5, latch 5
;; depth 1, outer 0
;; nodes: 5
;;
;; Loop 1
;; header 3, latch 3
;; depth 1, outer 0
;; nodes: 3
;; 2 succs { 3 }
;; 3 succs { 3 4 }
;; 4 succs { 5 }
;; 5 succs { 5 6 }
;; 6 succs { 7 8 }
;; 7 succs { }
;; 8 succs { 1 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 9 n_edges 10 count 11 ( 1.2)
main
Dataflow summary:
def_info->table_size = 187, use_info->table_size = 67
;; invalidated by call 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave]
;; hardware regs used 1 [1] 67 [ap] 113 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 65 [lr] 67 [ap] 113 [sfp]
;; exit block uses 1 [1] 3 [3] 31 [31] 113 [sfp]
;; regs ever live 1[1] 3[3] 4[4] 5[5] 65[lr]
;; ref usage r0={2d} r1={1d,10u} r2={2d} r3={5d,3u} r4={4d,1u} r5={4d,1u} r6={3d} r7={3d} r8={3d} r9={3d} r10={3d} r11={3d} r12={2d} r13={2d} r31={1d,8u} r32={2d} r33={3d} r34={3d} r35={3d} r36={3d} r37={3d} r38={3d} r39={3d} r40={3d} r41={2d} r42={2d} r43={2d} r44={2d} r45={2d} r64={2d} r65={3d} r66={2d} r67={1d,7u} r68={2d} r69={2d} r73={2d} r74={2d} r75={2d} r76={2d} r77={2d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r84={2d} r85={2d} r86={2d} r87={2d} r88={2d} r89={2d} r90={2d} r91={2d} r92={2d} r93={2d} r94={2d} r95={2d} r96={2d} r97={2d} r98={2d} r99={2d} r100={2d} r101={2d} r102={2d} r103={2d} r104={2d} r105={2d} r106={2d} r107={2d} r108={2d} r109={2d} r113={1d,8u} r121={2d,3u} r122={2d,2u} r123={2d,2u,1d} r124={2d,3u} r131={1d,2u} r132={1d,1u} r138={1d,1u} r142={1d,1u} r143={1d,1u} r145={1d,1u} r147={1d,2u} r148={1d,2u} r150={1d,1u} r154={1d,1u} r155={1d,1u} r156={2d,2u} r157={2d,2u} r158={1d,1u}
;; total ref usage 256{188d,67u,1e} in 34{32 regular + 2 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d2(1){ }d9(3){ }d13(4){ }d17(5){ }d20(6){ }d23(7){ }d26(8){ }d29(9){ }d32(10){ }d35(11){ }d40(31){ }d45(33){ }d48(34){ }d51(35){ }d54(36){ }d57(37){ }d60(38){ }d63(39){ }d66(40){ }d81(65){ }d84(67){ }d163(113){ }}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 65 [lr] 67 [ap] 113 [sfp]
;; live in
;; live gen 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 65 [lr] 67 [ap] 113 [sfp]
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
( 0 )->[2]->( 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ }u1(31){ }u2(67){ }u3(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def 121 124 145 147 148 150 154 155 157
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen 121 124 145 147 148 150 154 155 157
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
( 3 2 )->[3]->( 3 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ }u9(31){ }u10(67){ }u11(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 157
;; lr def 121 124 157
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; live gen 121 124 157
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
( 3 )->[4]->( 5 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(1){ }u23(31){ }u24(67){ }u25(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 154 155
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 154 155
;; lr def 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave] 122 123 131 132 156
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 154 155
;; live gen 3 [3] 4 [4] 5 [5] 122 123 131 132 156
;; live kill 65 [lr]
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
( 5 4 )->[5]->( 5 6 )
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u35(1){ }u36(31){ }u37(67){ }u38(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; lr def 122 123 138 156
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; live gen 122 123 138 156
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
( 5 )->[6]->( 7 8 )
;; bb 6 artificial_defs: { }
;; bb 6 artificial_uses: { u45(1){ }u46(31){ }u47(67){ }u48(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 123
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 123
;; lr def 142 143 158
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 123
;; live gen 142 143
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
( 6 )->[7]->( )
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u53(1){ }u54(31){ }u55(67){ }u56(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave]
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen
;; live kill 65 [lr]
;; lr out 1 [1] 67 [ap] 113 [sfp]
;; live out 1 [1] 67 [ap] 113 [sfp]
( 6 )->[8]->( 1 )
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u58(1){ }u59(31){ }u60(67){ }u61(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def 3 [3]
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen 3 [3]
;; live kill
;; lr out 1 [1] 3 [3] 31 [31] 67 [ap] 113 [sfp]
;; live out 1 [1] 3 [3] 31 [31] 67 [ap] 113 [sfp]
( 8 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u63(1){ }u64(3){ }u65(31){ }u66(113){ }}
;; lr in 1 [1] 3 [3] 31 [31] 113 [sfp]
;; lr use 1 [1] 3 [3] 31 [31] 113 [sfp]
;; lr def
;; live in 1 [1] 3 [3] 31 [31] 113 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 90 to worklist
Adding insn 15 to worklist
Adding insn 12 to worklist
Adding insn 31 to worklist
Adding insn 88 to worklist
Adding insn 47 to worklist
Adding insn 49 to worklist
Adding insn 63 to worklist
Finished finding needed instructions:
processing block 7 lr out = 1 [1] 67 [ap] 113 [sfp]
processing block 8 lr out = 1 [1] 3 [3] 31 [31] 67 [ap] 113 [sfp]
Adding insn 57 to worklist
processing block 6 lr out = 1 [1] 31 [31] 67 [ap] 113 [sfp]
Adding insn 46 to worklist
Adding insn 94 to worklist
Adding insn 93 to worklist
processing block 5 lr out = 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
Adding insn 38 to worklist
Adding insn 37 to worklist
Adding insn 36 to worklist
processing block 4 lr out = 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
Adding insn 89 to worklist
Adding insn 34 to worklist
Adding insn 33 to worklist
Adding insn 30 to worklist
Adding insn 29 to worklist
Adding insn 28 to worklist
Adding insn 23 to worklist
Adding insn 22 to worklist
processing block 3 lr out = 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
Adding insn 17 to worklist
Adding insn 16 to worklist
processing block 2 lr out = 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
Adding insn 91 to worklist
Adding insn 69 to worklist
Adding insn 70 to worklist
Adding insn 78 to worklist
Adding insn 76 to worklist
Adding insn 75 to worklist
Adding insn 73 to worklist
Adding insn 8 to worklist
Adding insn 7 to worklist
df_worklist_dataflow_doublequeue:n_basic_blocks 9 n_edges 10 count 16 ( 1.8)
df_worklist_dataflow_doublequeue:n_basic_blocks 9 n_edges 10 count 16 ( 1.8)
SMS analysis phase
===================
SMS loop num: 2, file: sms-6.c, line: 30
...OK
SMS loop num: 1, file: sms-6.c, line: 23
...OK
SMS transformation phase
=========================
SMS loop num: 2, file: sms-6.c, line: 30
Node num: 0
(insn:HI 36 35 37 5 sms-6.c:32 (set (reg:SI 138)
(mem/s:SI (reg/f:SI 122 [ ivtmp.82 ]) [2 a S4 A32])) 334 {*movsi_internal1} (nil))
OUT ARCS: [36 -(A,0,0)-> 38] [36 -(T,2,0)-> 37]
IN ARCS: [37 -(A,0,1)-> 36] [38 -(T,1,1)-> 36]
Node num: 1
(insn:HI 37 36 38 5 sms-6.c:32 (set (reg/v:SI 123 [ res ])
(plus:SI (reg/v:SI 123 [ res ])
(reg:SI 138))) 82 {*addsi3_internal1} (expr_list:REG_DEAD (reg:SI 138)
(nil)))
OUT ARCS: [37 -(A,0,1)-> 36] [37 -(T,1,1)-> 37]
IN ARCS: [37 -(T,1,1)-> 37] [36 -(T,2,0)-> 37]
Node num: 2
(insn:HI 38 37 88 5 sms-6.c:32 (set (reg/f:SI 122 [ ivtmp.82 ])
(plus:SI (reg/f:SI 122 [ ivtmp.82 ])
(const_int 4 [0x4]))) 82 {*addsi3_internal1} (nil))
OUT ARCS: [38 -(T,1,1)-> 36] [38 -(T,1,1)-> 38]
IN ARCS: [38 -(T,1,1)-> 38] [36 -(A,0,0)-> 38]
Node num: 3
(jump_insn:HI 88 38 44 5 sms-6.c:30 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 156)
(const_int 1 [0x1]))
(label_ref:SI 39)
(pc)))
(set (reg:SI 156)
(plus:SI (reg:SI 156)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9899 [0x26ab])
(nil)))
OUT ARCS: [88 -(T,1,1)-> 88] [88 -(T,1,1)-> 88]
IN ARCS: [88 -(T,1,1)-> 88] [88 -(T,1,1)-> 88]
sms-6.c 30 (file, line)
SMS single-bb-loop
SMS doloop
SMS built-ddg 4
SMS num-loads 1
SMS num-stores 0
SMS const-doloop 100
Order params
node 0, ASAP: 0, ALAP: 0, HEIGHT: 2
node 1, ASAP: 2, ALAP: 2, HEIGHT: 0
node 2, ASAP: 0, ALAP: 2, HEIGHT: 0
node 3, ASAP: 0, ALAP: 2, HEIGHT: 0
;; Number of SCC nodes - 2
SCC number: 0
insn num 0
(insn:HI 36 35 37 5 sms-6.c:32 (set (reg:SI 138)
(mem/s:SI (reg/f:SI 122 [ ivtmp.82 ]) [2 a S4 A32])) 334 {*movsi_internal1} (nil))
insn num 1
(insn:HI 37 36 38 5 sms-6.c:32 (set (reg/v:SI 123 [ res ])
(plus:SI (reg/v:SI 123 [ res ])
(reg:SI 138))) 82 {*addsi3_internal1} (expr_list:REG_DEAD (reg:SI 138)
(nil)))
insn num 2
(insn:HI 38 37 88 5 sms-6.c:32 (set (reg/f:SI 122 [ ivtmp.82 ])
(plus:SI (reg/f:SI 122 [ ivtmp.82 ])
(const_int 4 [0x4]))) 82 {*addsi3_internal1} (nil))
SCC number: 1
insn num 3
(jump_insn:HI 88 38 44 5 sms-6.c:30 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 156)
(const_int 1 [0x1]))
(label_ref:SI 39)
(pc)))
(set (reg:SI 156)
(plus:SI (reg:SI 156)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9899 [0x26ab])
(nil)))
SMS final nodes order:
1 0 2 3
SMS iis 2 4 8 (rec_mii, mii, maxii)
Starting with ii=4
Trying to schedule node 1 INSN = 37 in (2 .. 6) step 1
must_precede:
must_follow:
Scheduled w/o split in 2
Processing edge: [37 -(A,0,1)-> 36]
Scheduling 0 (36) in psp_pss_not_empty, checking p 1 (37): pred st = 2; early_start = -2; latency = 0
Processing edge: [38 -(T,1,1)-> 36]
Scheduling 0 (36) in psp_pss_not_empty, checking p 2 (38): the node is not scheduled
Processing edge: [36 -(A,0,0)-> 38]
Scheduling 0 (36) in psp_pss_not_empty, checking s 2 (38): the node is not scheduled
Processing edge: [36 -(T,2,0)-> 37]
Scheduling 0 (36) in psp_pss_not_empty, checking s 1 (37): succ st = 2; late_start = 0; latency = 2
Trying to schedule node 0 INSN = 36 in (0 .. -3) step -1
must_precede: 1
must_follow:
Scheduled w/o split in 0
Processing edge: [38 -(T,1,1)-> 38]
Scheduling 2 (38) in psp_pss_not_empty, checking p 2 (38): the node is not scheduled
Processing edge: [36 -(A,0,0)-> 38]
Scheduling 2 (38) in psp_pss_not_empty, checking p 0 (36): pred st = 0; early_start = 0; latency = 0
Processing edge: [38 -(T,1,1)-> 36]
Scheduling 2 (38) in psp_pss_not_empty, checking s 0 (36): succ st = 0; late_start = 3; latency = 1
Processing edge: [38 -(T,1,1)-> 38]
Scheduling 2 (38) in psp_pss_not_empty, checking s 2 (38): the node is not scheduled
Trying to schedule node 2 INSN = 38 in (3 .. -1) step -1
must_precede: 0
must_follow:
Scheduled w/o split in 3
SMS succeeded 4 1 (with ii, sc)
[ROW 0 ]: 36,
[ROW 1 ]:
[ROW 2 ]: 37,
[ROW 3 ]: 38, SMS Branch (3) will later be scheduled at cycle -1.
crr_insn->node=0, crr_insn->cycle=0, min_cycle=0
crr_insn->node=1, crr_insn->cycle=2, min_cycle=0
crr_insn->node=2, crr_insn->cycle=3, min_cycle=0
changing bb of uid 96
unscanned insn
verify found no changes in insn with uid = 88.
Edge 5->5 redirected to 9
Node = 0; INSN = 36
asap = 0:
time = 0:
nreg_moves = 0:
Node = 1; INSN = 37
asap = 2:
time = 2:
nreg_moves = 0:
Node = 2; INSN = 38
asap = 0:
time = 3:
nreg_moves = 0:
Node = 3; INSN = 88
asap = 0:
time = 0:
nreg_moves = 0:
SMS loop num: 1, file: sms-6.c, line: 23
Node num: 0
(insn:HI 12 9 15 3 sms-6.c:25 (set (mem/s:SI (plus:SI (reg/f:SI 148)
(reg:SI 121 [ ivtmp.91 ])) [2 c S4 A32])
(reg/v:SI 124 [ i ])) 334 {*movsi_internal1} (nil))
OUT ARCS: [12 -(O,0,0)-> 90] [12 -(A,0,0)-> 17] [12 -(A,0,0)-> 16]
IN ARCS: [16 -(T,1,1)-> 12] [17 -(T,1,1)-> 12] [15 -(O,0,1)-> 12]
Node num: 1
(insn:HI 15 12 16 3 sms-6.c:25 (set (mem/s:SI (plus:SI (reg/f:SI 147)
(reg:SI 121 [ ivtmp.91 ])) [2 b S4 A32])
(reg/v:SI 124 [ i ])) 334 {*movsi_internal1} (nil))
OUT ARCS: [15 -(O,0,0)-> 90] [15 -(A,0,0)-> 17] [15 -(A,0,0)-> 16] [15 -(O,0,1)-> 12]
IN ARCS: [16 -(T,1,1)-> 15] [17 -(T,1,1)-> 15]
Node num: 2
(insn:HI 16 15 17 3 sms-6.c:23 (set (reg/v:SI 124 [ i ])
(plus:SI (reg/v:SI 124 [ i ])
(const_int 1 [0x1]))) 82 {*addsi3_internal1} (nil))
OUT ARCS: [16 -(T,1,1)-> 12] [16 -(T,1,1)-> 15] [16 -(T,1,1)-> 16]
IN ARCS: [16 -(T,1,1)-> 16] [15 -(A,0,0)-> 16] [12 -(A,0,0)-> 16]
Node num: 3
(insn:HI 17 16 90 3 sms-6.c:23 (set (reg:SI 121 [ ivtmp.91 ])
(plus:SI (reg:SI 121 [ ivtmp.91 ])
(const_int 4 [0x4]))) 82 {*addsi3_internal1} (nil))
OUT ARCS: [17 -(T,1,1)-> 12] [17 -(T,1,1)-> 15] [17 -(T,1,1)-> 17]
IN ARCS: [17 -(T,1,1)-> 17] [15 -(A,0,0)-> 17] [12 -(A,0,0)-> 17]
Node num: 4
(jump_insn:HI 90 17 21 3 sms-6.c:23 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 157)
(const_int 1 [0x1]))
(label_ref:SI 18)
(pc)))
(set (reg:SI 157)
(plus:SI (reg:SI 157)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9899 [0x26ab])
(nil)))
OUT ARCS: [90 -(T,1,1)-> 90] [90 -(T,1,1)-> 90]
IN ARCS: [90 -(T,1,1)-> 90] [90 -(T,1,1)-> 90] [15 -(O,0,0)-> 90] [12 -(O,0,0)-> 90]
sms-6.c 23 (file, line)
SMS single-bb-loop
SMS doloop
SMS built-ddg 5
SMS num-loads 0
SMS num-stores 2
SMS const-doloop 100
Order params
node 0, ASAP: 0, ALAP: 0, HEIGHT: 0
node 1, ASAP: 0, ALAP: 0, HEIGHT: 0
node 2, ASAP: 0, ALAP: 0, HEIGHT: 0
node 3, ASAP: 0, ALAP: 0, HEIGHT: 0
node 4, ASAP: 0, ALAP: 0, HEIGHT: 0
;; Number of SCC nodes - 2
SCC number: 0
insn num 0
(insn:HI 12 9 15 3 sms-6.c:25 (set (mem/s:SI (plus:SI (reg/f:SI 148)
(reg:SI 121 [ ivtmp.91 ])) [2 c S4 A32])
(reg/v:SI 124 [ i ])) 334 {*movsi_internal1} (nil))
insn num 1
(insn:HI 15 12 16 3 sms-6.c:25 (set (mem/s:SI (plus:SI (reg/f:SI 147)
(reg:SI 121 [ ivtmp.91 ])) [2 b S4 A32])
(reg/v:SI 124 [ i ])) 334 {*movsi_internal1} (nil))
insn num 2
(insn:HI 16 15 17 3 sms-6.c:23 (set (reg/v:SI 124 [ i ])
(plus:SI (reg/v:SI 124 [ i ])
(const_int 1 [0x1]))) 82 {*addsi3_internal1} (nil))
insn num 3
(insn:HI 17 16 90 3 sms-6.c:23 (set (reg:SI 121 [ ivtmp.91 ])
(plus:SI (reg:SI 121 [ ivtmp.91 ])
(const_int 4 [0x4]))) 82 {*addsi3_internal1} (nil))
SCC number: 1
insn num 4
(jump_insn:HI 90 17 21 3 sms-6.c:23 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 157)
(const_int 1 [0x1]))
(label_ref:SI 18)
(pc)))
(set (reg:SI 157)
(plus:SI (reg:SI 157)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 588 {*ctrsi_internal1} (expr_list:REG_BR_PROB (const_int 9899 [0x26ab])
(nil)))
SMS final nodes order:
0 1 2 3 4
SMS iis 1 5 10 (rec_mii, mii, maxii)
Starting with ii=5
Trying to schedule node 0 INSN = 12 in (0 .. 5) step 1
must_precede:
must_follow:
Scheduled w/o split in 0
Processing edge: [15 -(O,0,0)-> 90]
Scheduling 1 (15) in pss_not_empty, checking s 4 (90): the node is not scheduled
Processing edge: [15 -(A,0,0)-> 17]
Scheduling 1 (15) in pss_not_empty, checking s 3 (17): the node is not scheduled
Processing edge: [15 -(A,0,0)-> 16]
Scheduling 1 (15) in pss_not_empty, checking s 2 (16): the node is not scheduled
Processing edge: [15 -(O,0,1)-> 12]
Scheduling 1 (15) in pss_not_empty, checking s 0 (12): succ st = 0; late_start = 5; latency = 0end = -4
Scheduling 1 (15) in a window (5..0) with step -1
Trying to schedule node 1 INSN = 15 in (5 .. 0) step -1
must_precede:
must_follow: 0
Scheduled w/o split in 4
Processing edge: [16 -(T,1,1)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking p 2 (16): the node is not scheduled
Processing edge: [15 -(A,0,0)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking p 1 (15): pred st = 4; early_start = 4; latency = 0
Processing edge: [12 -(A,0,0)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking p 0 (12): pred st = 0; early_start = 4; latency = 0
Processing edge: [16 -(T,1,1)-> 12]
Scheduling 2 (16) in psp_pss_not_empty, checking s 0 (12): succ st = 0; late_start = 4; latency = 1
Processing edge: [16 -(T,1,1)-> 15]
Scheduling 2 (16) in psp_pss_not_empty, checking s 1 (15): succ st = 4; late_start = 4; latency = 1
Processing edge: [16 -(T,1,1)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking s 2 (16): the node is not scheduled
Trying to schedule node 2 INSN = 16 in (4 .. 3) step -1
must_precede: 1
must_follow:
split_row=0
crr_insn->node=0, crr_insn->cycle=0, min_cycle=0
crr_insn->node=1, crr_insn->cycle=4, min_cycle=0
min_cycle=1, max_cycle=5
num_splits=1
Processing edge: [16 -(T,1,1)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking p 2 (16): the node is not scheduled
Processing edge: [15 -(A,0,0)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking p 1 (15): pred st = 5; early_start = 5; latency = 0
Processing edge: [12 -(A,0,0)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking p 0 (12): pred st = 1; early_start = 5; latency = 0
Processing edge: [16 -(T,1,1)-> 12]
Scheduling 2 (16) in psp_pss_not_empty, checking s 0 (12): succ st = 1; late_start = 6; latency = 1
Processing edge: [16 -(T,1,1)-> 15]
Scheduling 2 (16) in psp_pss_not_empty, checking s 1 (15): succ st = 5; late_start = 6; latency = 1
Processing edge: [16 -(T,1,1)-> 16]
Scheduling 2 (16) in psp_pss_not_empty, checking s 2 (16): the node is not scheduled
Trying to schedule node 2 INSN = 16 in (6 .. 4) step -1
must_precede: 1
must_follow:
Scheduled w/o split in 6
Processing edge: [17 -(T,1,1)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking p 3 (17): the node is not scheduled
Processing edge: [15 -(A,0,0)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking p 1 (15): pred st = 5; early_start = 5; latency = 0
Processing edge: [12 -(A,0,0)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking p 0 (12): pred st = 1; early_start = 5; latency = 0
Processing edge: [17 -(T,1,1)-> 12]
Scheduling 3 (17) in psp_pss_not_empty, checking s 0 (12): succ st = 1; late_start = 6; latency = 1
Processing edge: [17 -(T,1,1)-> 15]
Scheduling 3 (17) in psp_pss_not_empty, checking s 1 (15): succ st = 5; late_start = 6; latency = 1
Processing edge: [17 -(T,1,1)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking s 3 (17): the node is not scheduled
Trying to schedule node 3 INSN = 17 in (6 .. 4) step -1
must_precede: 1
must_follow:
split_row=0
crr_insn->node=2, crr_insn->cycle=6, min_cycle=1
crr_insn->node=0, crr_insn->cycle=1, min_cycle=1
crr_insn->node=1, crr_insn->cycle=5, min_cycle=1
min_cycle=1, max_cycle=6
num_splits=1
Processing edge: [17 -(T,1,1)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking p 3 (17): the node is not scheduled
Processing edge: [15 -(A,0,0)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking p 1 (15): pred st = 5; early_start = 5; latency = 0
Processing edge: [12 -(A,0,0)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking p 0 (12): pred st = 1; early_start = 5; latency = 0
Processing edge: [17 -(T,1,1)-> 12]
Scheduling 3 (17) in psp_pss_not_empty, checking s 0 (12): succ st = 1; late_start = 7; latency = 1
Processing edge: [17 -(T,1,1)-> 15]
Scheduling 3 (17) in psp_pss_not_empty, checking s 1 (15): succ st = 5; late_start = 7; latency = 1
Processing edge: [17 -(T,1,1)-> 17]
Scheduling 3 (17) in psp_pss_not_empty, checking s 3 (17): the node is not scheduled
Trying to schedule node 3 INSN = 17 in (7 .. 4) step -1
must_precede: 1
must_follow:
Scheduled w/o split in 7
SMS succeeded 7 1 (with ii, sc)
[ROW 0 ]: 17,
[ROW 1 ]: 12,
[ROW 2 ]:
[ROW 3 ]:
[ROW 4 ]:
[ROW 5 ]: 15,
[ROW 6 ]: 16, SMS Branch (4) will later be scheduled at cycle 0.
crr_insn->node=3, crr_insn->cycle=7, min_cycle=1
crr_insn->node=0, crr_insn->cycle=1, min_cycle=1
crr_insn->node=1, crr_insn->cycle=5, min_cycle=1
crr_insn->node=2, crr_insn->cycle=6, min_cycle=1
changing bb of uid 98
unscanned insn
verify found no changes in insn with uid = 90.
Edge 3->3 redirected to 10
Node = 0; INSN = 12
asap = 0:
time = 0:
nreg_moves = 0:
Node = 1; INSN = 15
asap = 0:
time = 4:
nreg_moves = 0:
Node = 2; INSN = 16
asap = 0:
time = 5:
nreg_moves = 0:
Node = 3; INSN = 17
asap = 0:
time = 6:
nreg_moves = 0:
Node = 4; INSN = 90
asap = 0:
time = 0:
nreg_moves = 0:
Emitting label for block 4
rescanning insn with uid = 90.
deleting insn with uid = 90.
scanning new insn with uid = 101.
Emitting label for block 6
rescanning insn with uid = 88.
deleting insn with uid = 88.
scanning new insn with uid = 104.
Reordered sequence:
2 bb 2 [100]
3 bb 3 [9900]
4 bb 10 [9800]
5 bb 4 [100]
6 bb 5 [9900]
7 bb 9 [9800]
8 bb 6 [100]
9 bb 7 [0]
10 bb 8 [100]
main
Dataflow summary:
;; invalidated by call 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave]
;; hardware regs used 1 [1] 67 [ap] 113 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 65 [lr] 67 [ap] 113 [sfp]
;; exit block uses 1 [1] 3 [3] 31 [31] 113 [sfp]
;; regs ever live 1[1] 3[3] 4[4] 5[5] 65[lr]
;; ref usage r0={2d} r1={1d,12u} r2={2d} r3={5d,3u} r4={4d,1u} r5={4d,1u} r6={3d} r7={3d} r8={3d} r9={3d} r10={3d} r11={3d} r12={2d} r13={2d} r31={1d,10u} r32={2d} r33={3d} r34={3d} r35={3d} r36={3d} r37={3d} r38={3d} r39={3d} r40={3d} r41={2d} r42={2d} r43={2d} r44={2d} r45={2d} r64={2d} r65={3d} r66={2d} r67={1d,9u} r68={2d} r69={2d} r73={2d} r74={2d} r75={2d} r76={2d} r77={2d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r84={2d} r85={2d} r86={2d} r87={2d} r88={2d} r89={2d} r90={2d} r91={2d} r92={2d} r93={2d} r94={2d} r95={2d} r96={2d} r97={2d} r98={2d} r99={2d} r100={2d} r101={2d} r102={2d} r103={2d} r104={2d} r105={2d} r106={2d} r107={2d} r108={2d} r109={2d} r113={1d,10u} r121={2d,3u} r122={2d,2u} r123={2d,2u,1d} r124={2d,3u} r131={1d,2u} r132={1d,1u} r138={1d,1u} r142={1d,1u} r143={1d,1u} r145={1d,1u} r147={1d,2u} r148={1d,2u} r150={1d,1u} r154={1d,1u} r155={1d,1u} r156={2d,2u} r157={2d,2u} r158={1d,1u}
;; total ref usage 264{188d,75u,1e} in 36{34 regular + 2 call} insns.
;; Reaching defs:
sparse invalidated
dense invalidated 0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162
0[0,2] 1[2,1] 2[3,2] 3[5,5] 4[10,4] 5[14,4] 6[18,3] 7[21,3] 8[24,3] 9[27,3] 10[30,3] 11[33,3] 12[36,2] 13[38,2] 31[40,1] 32[41,2] 33[43,3] 34[46,3] 35[49,3] 36[52,3] 37[55,3] 38[58,3] 39[61,3] 40[64,3] 41[67,2] 42[69,2] 43[71,2] 44[73,2] 45[75,2] 64[77,2] 65[79,3] 66[82,2] 67[84,1] 68[85,2] 69[87,2] 73[89,2] 74[91,2] 75[93,2] 76[95,2] 77[97,2] 78[99,2] 79[101,2] 80[103,2] 81[105,2] 82[107,2] 83[109,2] 84[111,2] 85[113,2] 86[115,2] 87[117,2] 88[119,2] 89[121,2] 90[123,2] 91[125,2] 92[127,2] 93[129,2] 94[131,2] 95[133,2] 96[135,2] 97[137,2] 98[139,2] 99[141,2] 100[143,2] 101[145,2] 102[147,2] 103[149,2] 104[151,2] 105[153,2] 106[155,2] 107[157,2] 108[159,2] 109[161,2] 113[163,1] 121[164,2] 122[166,2] 123[168,2] 124[170,2] 131[172,1] 132[173,1] 138[174,1] 142[175,1] 143[176,1] 145[177,1] 147[178,1] 148[179,1] 150[180,1] 154[181,1] 155[182,1] 156[183,2] 157[185,2] 158[187,1]
(note:HI 3 0 5 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ d2(bb 0 insn -1) }u1(31){ d40(bb 0 insn -1) }u2(67){ d84(bb 0 insn -1) }u3(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def 121 124 145 147 148 150 154 155 157
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen 121 124 145 147 148 150 154 155 157
;; live kill
;; rd in (22)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 81, 84, 163
;; rd gen (9)
165, 171, 177, 178, 179, 180, 181, 182, 185
;; rd kill (12)
164, 165, 170, 171, 177, 178, 179, 180, 181, 182, 185, 186
;; DU chains for insn luid 0 uid 7
;; reg 121 { u19(bb 3 insn 17) u15(bb 3 insn 15) u12(bb 3 insn 12) }
;; DU chains for insn luid 1 uid 8
;; reg 124 { u18(bb 3 insn 16) u16(bb 3 insn 15) u13(bb 3 insn 12) }
;; DU chains for insn luid 2 uid 73
;; reg 145 { u4(bb 2 insn 75) }
;; DU chains for insn luid 3 uid 75
;; reg 148 { u14(bb 3 insn 12) u6(bb 2 insn 70) }
;; DU chains for insn luid 4 uid 76
;; reg 150 { u5(bb 2 insn 78) }
;; DU chains for insn luid 5 uid 78
;; reg 147 { u17(bb 3 insn 15) u7(bb 2 insn 69) }
;; DU chains for insn luid 6 uid 70
;; reg 154 { u29(bb 5 insn 30) }
;; DU chains for insn luid 7 uid 69
;; reg 155 { u28(bb 5 insn 29) }
;; DU chains for insn luid 8 uid 91
;; reg 157 { }
;; Pred edge ENTRY [100.0%] (fallthru)
(note:HI 5 3 4 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note:HI 4 5 7 2 NOTE_INSN_FUNCTION_BEG)
(insn:HI 7 4 8 2 sms-6.c:21 (set (reg:SI 121 [ ivtmp.91 ])
(const_int 0 [0x0])) 334 {*movsi_internal1} (nil))
(insn:HI 8 7 73 2 sms-6.c:21 (set (reg/v:SI 124 [ i ])
(const_int 0 [0x0])) 334 {*movsi_internal1} (nil))
(insn:HI 73 8 75 2 (set (reg/f:SI 145)
(high:SI (symbol_ref:SI ("c") [flags 0x80] <var_decl 0x2a95671640 c>))) 437 {elf_high} (nil))
(insn:HI 75 73 76 2 (set (reg/f:SI 148)
(lo_sum:SI (reg/f:SI 145)
(symbol_ref:SI ("c") [flags 0x80] <var_decl 0x2a95671640 c>))) 438 {elf_low} (expr_list:REG_DEAD (reg/f:SI 145)
(expr_list:REG_EQUAL (symbol_ref:SI ("c") [flags 0x80] <var_decl 0x2a95671640 c>)
(nil))))
(insn:HI 76 75 78 2 (set (reg/f:SI 150)
(high:SI (symbol_ref:SI ("b") [flags 0x80] <var_decl 0x2a956715a0 b>))) 437 {elf_high} (nil))
(insn:HI 78 76 70 2 (set (reg/f:SI 147)
(lo_sum:SI (reg/f:SI 150)
(symbol_ref:SI ("b") [flags 0x80] <var_decl 0x2a956715a0 b>))) 438 {elf_low} (expr_list:REG_DEAD (reg/f:SI 150)
(expr_list:REG_EQUAL (symbol_ref:SI ("b") [flags 0x80] <var_decl 0x2a956715a0 b>)
(nil))))
(insn:HI 70 78 69 2 sms-6.c:25 (set (reg/f:SI 154)
(reg/f:SI 148)) 334 {*movsi_internal1} (expr_list:REG_EQUAL (symbol_ref:SI ("c") [flags 0x80] <var_decl 0x2a95671640 c>)
(nil)))
(insn:HI 69 70 91 2 sms-6.c:25 (set (reg/f:SI 155)
(reg/f:SI 147)) 334 {*movsi_internal1} (expr_list:REG_EQUAL (symbol_ref:SI ("b") [flags 0x80] <var_decl 0x2a956715a0 b>)
(nil)))
(insn:HI 91 69 18 2 sms-6.c:25 (set (reg:SI 157)
(const_int 100 [0x64])) 334 {*movsi_internal1} (nil))
;; End of basic block 2 -> ( 3)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; rd out (31)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 81, 84, 163, 165, 171, 177, 178, 179, 180, 181, 182, 185
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 3 uid 75
;; reg 145 { d177(bb 2 insn 73) }
;; UD chains for insn luid 5 uid 78
;; reg 150 { d180(bb 2 insn 76) }
;; UD chains for insn luid 6 uid 70
;; reg 148 { d179(bb 2 insn 75) }
;; UD chains for insn luid 7 uid 69
;; reg 147 { d178(bb 2 insn 78) }
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 2 4) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ d2(bb 0 insn -1) }u9(31){ d40(bb 0 insn -1) }u10(67){ d84(bb 0 insn -1) }u11(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 157
;; lr def 121 124 157
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; live gen 121 124 157
;; live kill
;; rd in (34)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 81, 84, 163, 164, 165, 170, 171, 177, 178, 179, 180, 181, 182, 185, 186
;; rd gen (3)
164, 170, 186
;; rd kill (6)
164, 165, 170, 171, 185, 186
;; DU chains for insn luid 2 uid 16
;; reg 124 { u18(bb 3 insn 16) u16(bb 3 insn 15) u13(bb 3 insn 12) }
;; DU chains for insn luid 3 uid 17
;; reg 121 { u19(bb 3 insn 17) u15(bb 3 insn 15) u12(bb 3 insn 12) }
;; DU chains for insn luid 0 uid 90
;; reg 157 { }
;; Pred edge 2 [100.0%] (fallthru)
;; Pred edge 4 [100.0%]
(code_label:HI 18 91 9 3 9 "" [1 uses])
(note:HI 9 18 12 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn:HI 12 9 15 3 sms-6.c:25 (set (mem/s:SI (plus:SI (reg/f:SI 148)
(reg:SI 121 [ ivtmp.91 ])) [2 c S4 A32])
(reg/v:SI 124 [ i ])) 334 {*movsi_internal1} (nil))
(insn:HI 15 12 16 3 sms-6.c:25 (set (mem/s:SI (plus:SI (reg/f:SI 147)
(reg:SI 121 [ ivtmp.91 ])) [2 b S4 A32])
(reg/v:SI 124 [ i ])) 334 {*movsi_internal1} (nil))
(insn:HI 16 15 17 3 sms-6.c:23 (set (reg/v:SI 124 [ i ])
(plus:SI (reg/v:SI 124 [ i ])
(const_int 1 [0x1]))) 82 {*addsi3_internal1} (nil))
(insn:HI 17 16 90 3 sms-6.c:23 (set (reg:SI 121 [ ivtmp.91 ])
(plus:SI (reg:SI 121 [ ivtmp.91 ])
(const_int 4 [0x4]))) 82 {*addsi3_internal1} (nil))
(jump_insn:HI 90 17 99 3 sms-6.c:23 (parallel [
(set (pc)
(if_then_else (eq (reg:SI 157)
(const_int 1 [0x1]))
(label_ref:SI 100)
(pc)))
(set (reg:SI 157)
(plus:SI (reg:SI 157)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 592 {*ctrsi_internal5} (expr_list:REG_BR_PROB (const_int 101 [0x65])
(nil)))
;; End of basic block 3 -> ( 4 5)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 121 124 147 148 154 155 157
;; rd out (31)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 81, 84, 163, 164, 170, 177, 178, 179, 180, 181, 182, 186
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 0 uid 12
;; reg 121 { d165(bb 2 insn 7) d164(bb 3 insn 17) }
;; reg 124 { d171(bb 2 insn 8) d170(bb 3 insn 16) }
;; reg 148 { d179(bb 2 insn 75) }
;; UD chains for insn luid 1 uid 15
;; reg 121 { d165(bb 2 insn 7) d164(bb 3 insn 17) }
;; reg 124 { d171(bb 2 insn 8) d170(bb 3 insn 16) }
;; reg 147 { d178(bb 2 insn 78) }
;; UD chains for insn luid 2 uid 16
;; reg 124 { d171(bb 2 insn 8) d170(bb 3 insn 16) }
;; UD chains for insn luid 3 uid 17
;; reg 121 { d165(bb 2 insn 7) d164(bb 3 insn 17) }
;; UD chains for insn luid 0 uid 90
;; reg 157 { }
;; reg 157 { }
;; Succ edge 4 [99.0%] (fallthru,dfs_back)
;; Succ edge 5 [1.0%] (loop_exit)
;; Start of basic block ( 3) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; Pred edge 3 [99.0%] (fallthru,dfs_back)
(code_label 99 90 98 4 16 "" [0 uses])
(note 98 99 101 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(jump_insn 101 98 102 4 (set (pc)
(label_ref 18)) -1 (nil))
;; End of basic block 4 -> ( 3)
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
;; Succ edge 3 [100.0%]
(barrier 102 101 100)
;; Start of basic block ( 3) -> 5
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u22(1){ d2(bb 0 insn -1) }u23(31){ d40(bb 0 insn -1) }u24(67){ d84(bb 0 insn -1) }u25(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 154 155
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 154 155
;; lr def 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave] 122 123 131 132 156
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 154 155
;; live gen 3 [3] 4 [4] 5 [5] 122 123 131 132 156
;; live kill 65 [lr]
;; rd in (31)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 81, 84, 163, 164, 170, 177, 178, 179, 180, 181, 182, 186
;; rd gen (5)
166, 169, 172, 173, 183
;; rd kill (11)
79, 80, 81, 166, 167, 168, 169, 172, 173, 183, 184
;; DU chains for insn luid 0 uid 22
;; reg 132 { u26(bb 5 insn 23) }
;; DU chains for insn luid 1 uid 23
;; reg 131 { u34(bb 5 insn 33) u27(bb 5 insn 28) }
;; DU chains for insn luid 2 uid 28
;; reg 3 { u31(bb 5 insn 31) }
;; DU chains for insn luid 3 uid 29
;; reg 4 { u32(bb 5 insn 31) }
;; DU chains for insn luid 4 uid 30
;; reg 5 { u33(bb 5 insn 31) }
;; DU chains for insn luid 5 uid 31
;; reg 0 { }
;; reg 2 { }
;; reg 3 { }
;; reg 4 { }
;; reg 5 { }
;; reg 6 { }
;; reg 7 { }
;; reg 8 { }
;; reg 9 { }
;; reg 10 { }
;; reg 11 { }
;; reg 12 { }
;; reg 13 { }
;; reg 32 { }
;; reg 33 { }
;; reg 34 { }
;; reg 35 { }
;; reg 36 { }
;; reg 37 { }
;; reg 38 { }
;; reg 39 { }
;; reg 40 { }
;; reg 41 { }
;; reg 42 { }
;; reg 43 { }
;; reg 44 { }
;; reg 45 { }
;; reg 64 { }
;; reg 66 { }
;; reg 68 { }
;; reg 69 { }
;; reg 73 { }
;; reg 74 { }
;; reg 75 { }
;; reg 76 { }
;; reg 77 { }
;; reg 78 { }
;; reg 79 { }
;; reg 80 { }
;; reg 81 { }
;; reg 82 { }
;; reg 83 { }
;; reg 84 { }
;; reg 85 { }
;; reg 86 { }
;; reg 87 { }
;; reg 88 { }
;; reg 89 { }
;; reg 90 { }
;; reg 91 { }
;; reg 92 { }
;; reg 93 { }
;; reg 94 { }
;; reg 95 { }
;; reg 96 { }
;; reg 97 { }
;; reg 98 { }
;; reg 99 { }
;; reg 100 { }
;; reg 101 { }
;; reg 102 { }
;; reg 103 { }
;; reg 104 { }
;; reg 105 { }
;; reg 106 { }
;; reg 107 { }
;; reg 108 { }
;; reg 109 { }
;; reg 65 { }
;; DU chains for insn luid 6 uid 33
;; reg 122 { u42(bb 6 insn 38) u39(bb 6 insn 36) }
;; DU chains for insn luid 7 uid 34
;; reg 123 { u40(bb 6 insn 37) }
;; DU chains for insn luid 8 uid 89
;; reg 156 { }
;; Pred edge 3 [1.0%] (loop_exit)
(code_label 100 102 21 5 17 "" [1 uses])
(note:HI 21 100 22 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn:HI 22 21 23 5 sms-6.c:27 (set (reg/f:SI 132)
(high:SI (symbol_ref:SI ("a") [flags 0x80] <var_decl 0x2a95671500 a>))) 437 {elf_high} (nil))
(insn:HI 23 22 28 5 sms-6.c:27 (set (reg/f:SI 131)
(lo_sum:SI (reg/f:SI 132)
(symbol_ref:SI ("a") [flags 0x80] <var_decl 0x2a95671500 a>))) 438 {elf_low} (expr_list:REG_DEAD (reg/f:SI 132)
(expr_list:REG_EQUAL (symbol_ref:SI ("a") [flags 0x80] <var_decl 0x2a95671500 a>)
(nil))))
(insn:HI 28 23 29 5 sms-6.c:27 (set (reg:SI 3 3)
(reg/f:SI 131)) 334 {*movsi_internal1} (expr_list:REG_EQUAL (symbol_ref:SI ("a") [flags 0x80] <var_decl 0x2a95671500 a>)
(nil)))
(insn:HI 29 28 30 5 sms-6.c:27 (set (reg:SI 4 4)
(reg/f:SI 155)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg/f:SI 155)
(expr_list:REG_EQUAL (symbol_ref:SI ("b") [flags 0x80] <var_decl 0x2a956715a0 b>)
(nil))))
(insn:HI 30 29 31 5 sms-6.c:27 (set (reg:SI 5 5)
(reg/f:SI 154)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg/f:SI 154)
(expr_list:REG_EQUAL (symbol_ref:SI ("c") [flags 0x80] <var_decl 0x2a95671640 c>)
(nil))))
(call_insn:HI 31 30 33 5 sms-6.c:27 (parallel [
(call (mem:SI (symbol_ref:SI ("foo") [flags 0x3] <function_decl 0x2a95658d00 foo>) [0 S4 A8])
(const_int 0 [0x0]))
(use (const_int 0 [0x0]))
(clobber (reg:SI 65 lr))
]) 439 {*call_local32} (expr_list:REG_DEAD (reg:SI 5 5)
(expr_list:REG_DEAD (reg:SI 4 4)
(expr_list:REG_DEAD (reg:SI 3 3)
(expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil)))))
(expr_list:REG_DEP_TRUE (use (reg:SI 5 5))
(expr_list:REG_DEP_TRUE (use (reg:SI 4 4))
(expr_list:REG_DEP_TRUE (use (reg:SI 3 3))
(nil)))))
(insn:HI 33 31 34 5 sms-6.c:27 (set (reg/f:SI 122 [ ivtmp.82 ])
(reg/f:SI 131)) 334 {*movsi_internal1} (expr_list:REG_DEAD (reg/f:SI 131)
(expr_list:REG_EQUAL (symbol_ref:SI ("a") [flags 0x80] <var_decl 0x2a95671500 a>)
(nil))))
(insn:HI 34 33 89 5 sms-6.c:27 (set (reg/v:SI 123 [ res ])
(const_int 0 [0x0])) 334 {*movsi_internal1} (nil))
(insn:HI 89 34 39 5 (set (reg:SI 156)
(const_int 100 [0x64])) 334 {*movsi_internal1} (nil))
;; End of basic block 5 -> ( 6)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; rd out (35)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 166, 169, 170, 172, 173, 177, 178, 179, 180, 181, 182, 183, 186
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 1 uid 23
;; reg 132 { d173(bb 5 insn 22) }
;; UD chains for insn luid 2 uid 28
;; reg 131 { d172(bb 5 insn 23) }
;; UD chains for insn luid 3 uid 29
;; reg 155 { d182(bb 2 insn 69) }
;; UD chains for insn luid 4 uid 30
;; reg 154 { d181(bb 2 insn 70) }
;; UD chains for insn luid 5 uid 31
;; reg 1 { d2(bb 0 insn -1) }
;; reg 3 { d8(bb 5 insn 28) }
;; reg 4 { d10(bb 5 insn 29) }
;; reg 5 { d14(bb 5 insn 30) }
;; UD chains for insn luid 6 uid 33
;; reg 131 { d172(bb 5 insn 23) }
;; Succ edge 6 [100.0%] (fallthru)
;; Start of basic block ( 5 7) -> 6
;; bb 6 artificial_defs: { }
;; bb 6 artificial_uses: { u35(1){ d2(bb 0 insn -1) }u36(31){ d40(bb 0 insn -1) }u37(67){ d84(bb 0 insn -1) }u38(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; lr def 122 123 138 156
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; live gen 122 123 138 156
;; live kill
;; rd in (39)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 166, 167, 168, 169, 170, 172, 173, 174, 177, 178, 179, 180, 181, 182, 183, 184, 186
;; rd gen (4)
167, 168, 174, 184
;; rd kill (7)
166, 167, 168, 169, 174, 183, 184
;; DU chains for insn luid 0 uid 36
;; reg 138 { u41(bb 6 insn 37) }
;; DU chains for insn luid 1 uid 37
;; reg 123 { u49(bb 8 insn 46) u40(bb 6 insn 37) }
;; DU chains for insn luid 2 uid 38
;; reg 122 { u42(bb 6 insn 38) u39(bb 6 insn 36) }
;; DU chains for insn luid 0 uid 88
;; reg 156 { }
;; Pred edge 5 [100.0%] (fallthru)
;; Pred edge 7 [100.0%]
(code_label:HI 39 89 35 6 10 "" [1 uses])
(note:HI 35 39 36 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn:HI 36 35 37 6 sms-6.c:32 (set (reg:SI 138)
(mem/s:SI (reg/f:SI 122 [ ivtmp.82 ]) [2 a S4 A32])) 334 {*movsi_internal1} (nil))
(insn:HI 37 36 38 6 sms-6.c:32 (set (reg/v:SI 123 [ res ])
(plus:SI (reg/v:SI 123 [ res ])
(reg:SI 138))) 82 {*addsi3_internal1} (expr_list:REG_DEAD (reg:SI 138)
(nil)))
(insn:HI 38 37 88 6 sms-6.c:32 (set (reg/f:SI 122 [ ivtmp.82 ])
(plus:SI (reg/f:SI 122 [ ivtmp.82 ])
(const_int 4 [0x4]))) 82 {*addsi3_internal1} (nil))
(jump_insn:HI 88 38 97 6 sms-6.c:30 (parallel [
(set (pc)
(if_then_else (eq (reg:SI 156)
(const_int 1 [0x1]))
(label_ref:SI 103)
(pc)))
(set (reg:SI 156)
(plus:SI (reg:SI 156)
(const_int -1 [0xffffffffffffffff])))
(clobber (scratch:CC))
(clobber (scratch:SI))
]) 592 {*ctrsi_internal5} (expr_list:REG_BR_PROB (const_int 101 [0x65])
(nil)))
;; End of basic block 6 -> ( 7 8)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 122 123 156
;; rd out (36)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 177, 178, 179, 180, 181, 182, 184, 186
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 0 uid 36
;; reg 122 { d167(bb 6 insn 38) d166(bb 5 insn 33) }
;; UD chains for insn luid 1 uid 37
;; reg 123 { d169(bb 5 insn 34) d168(bb 6 insn 37) }
;; reg 138 { d174(bb 6 insn 36) }
;; UD chains for insn luid 2 uid 38
;; reg 122 { d167(bb 6 insn 38) d166(bb 5 insn 33) }
;; UD chains for insn luid 0 uid 88
;; reg 156 { }
;; reg 156 { }
;; Succ edge 7 [99.0%] (fallthru,dfs_back)
;; Succ edge 8 [1.0%] (loop_exit)
;; Start of basic block ( 6) -> 7
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; Pred edge 6 [99.0%] (fallthru,dfs_back)
(code_label 97 88 96 7 15 "" [0 uses])
(note 96 97 104 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(jump_insn 104 96 105 7 (set (pc)
(label_ref 39)) -1 (nil))
;; End of basic block 7 -> ( 6)
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
;; Succ edge 6 [100.0%]
(barrier 105 104 103)
;; Start of basic block ( 6) -> 8
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u45(1){ d2(bb 0 insn -1) }u46(31){ d40(bb 0 insn -1) }u47(67){ d84(bb 0 insn -1) }u48(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 123
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 123
;; lr def 142 143 158
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp] 123
;; live gen 142 143 158
;; live kill
;; rd in (36)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 177, 178, 179, 180, 181, 182, 184, 186
;; rd gen (3)
175, 176, 187
;; rd kill (3)
175, 176, 187
;; DU chains for insn luid 0 uid 93
;; reg 158 { u-1(bb 8 insn 94) }
;; DU chains for insn luid 1 uid 94
;; reg 142 { u50(bb 8 insn 46) }
;; DU chains for insn luid 2 uid 46
;; reg 143 { u52(bb 8 insn 47) }
;; Pred edge 6 [1.0%] (loop_exit)
(code_label 103 105 44 8 18 "" [1 uses])
(note:HI 44 103 93 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 93 44 94 8 sms-6.c:34 (set (reg:SI 158)
(const_int 327680 [0x50000])) -1 (nil))
(insn 94 93 46 8 sms-6.c:34 (set (reg:SI 142)
(ior:SI (reg:SI 158)
(const_int 670 [0x29e]))) -1 (expr_list:REG_DEAD (reg:SI 158)
(expr_list:REG_EQUAL (const_int 328350 [0x5029e])
(nil))))
(insn:HI 46 94 47 8 sms-6.c:34 (set (reg:CC 143)
(compare:CC (reg/v:SI 123 [ res ])
(reg:SI 142))) 484 {*cmpsi_internal1} (expr_list:REG_DEAD (reg:SI 142)
(expr_list:REG_DEAD (reg/v:SI 123 [ res ])
(expr_list:REG_EQUAL (compare:CC (reg/v:SI 123 [ res ])
(const_int 328350 [0x5029e]))
(nil)))))
(jump_insn:HI 47 46 48 8 sms-6.c:34 (set (pc)
(if_then_else (eq (reg:CC 143)
(const_int 0 [0x0]))
(label_ref 51)
(pc))) 573 {*rs6000.md:14186} (expr_list:REG_DEAD (reg:CC 143)
(expr_list:REG_BR_PROB (const_int 9996 [0x270c])
(nil))))
;; End of basic block 8 -> ( 9 10)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; rd out (39)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 184, 186, 187
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 1 uid 94
;; reg 158 { d187(bb 8 insn 93) }
;; UD chains for insn luid 2 uid 46
;; reg 123 { d168(bb 6 insn 37) }
;; reg 142 { d175(bb 8 insn 94) }
;; eq_note reg 123 { }
;; UD chains for insn luid 3 uid 47
;; reg 143 { d176(bb 8 insn 46) }
;; Succ edge 9 [0.0%] (fallthru)
;; Succ edge 10 [100.0%]
;; Start of basic block ( 8) -> 9
;; bb 9 artificial_defs: { }
;; bb 9 artificial_uses: { u53(1){ d2(bb 0 insn -1) }u54(31){ d40(bb 0 insn -1) }u55(67){ d84(bb 0 insn -1) }u56(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66 [ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91 [14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 97 [20] 98 [21] 99 [22] 100 [23] 101 [24] 102 [25] 103 [26] 104 [27] 105 [28] 106 [29] 107 [30] 108 [31] 109 [vrsave]
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen
;; live kill 65 [lr]
;; rd in (39)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 184, 186, 187
;; rd gen (0)
;; rd kill (3)
79, 80, 81
;; DU chains for insn luid 0 uid 49
;; reg 0 { }
;; reg 2 { }
;; reg 3 { }
;; reg 4 { }
;; reg 5 { }
;; reg 6 { }
;; reg 7 { }
;; reg 8 { }
;; reg 9 { }
;; reg 10 { }
;; reg 11 { }
;; reg 12 { }
;; reg 13 { }
;; reg 32 { }
;; reg 33 { }
;; reg 34 { }
;; reg 35 { }
;; reg 36 { }
;; reg 37 { }
;; reg 38 { }
;; reg 39 { }
;; reg 40 { }
;; reg 41 { }
;; reg 42 { }
;; reg 43 { }
;; reg 44 { }
;; reg 45 { }
;; reg 64 { }
;; reg 66 { }
;; reg 68 { }
;; reg 69 { }
;; reg 73 { }
;; reg 74 { }
;; reg 75 { }
;; reg 76 { }
;; reg 77 { }
;; reg 78 { }
;; reg 79 { }
;; reg 80 { }
;; reg 81 { }
;; reg 82 { }
;; reg 83 { }
;; reg 84 { }
;; reg 85 { }
;; reg 86 { }
;; reg 87 { }
;; reg 88 { }
;; reg 89 { }
;; reg 90 { }
;; reg 91 { }
;; reg 92 { }
;; reg 93 { }
;; reg 94 { }
;; reg 95 { }
;; reg 96 { }
;; reg 97 { }
;; reg 98 { }
;; reg 99 { }
;; reg 100 { }
;; reg 101 { }
;; reg 102 { }
;; reg 103 { }
;; reg 104 { }
;; reg 105 { }
;; reg 106 { }
;; reg 107 { }
;; reg 108 { }
;; reg 109 { }
;; reg 65 { }
;; Pred edge 8 [0.0%] (fallthru)
(note:HI 48 47 49 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(call_insn:HI 49 48 50 9 sms-6.c:35 (parallel [
(call (mem:SI (symbol_ref:SI ("abort") [flags 0x41] <function_decl 0x2a9561ae00 abort>) [0 S4 A8])
(const_int 0 [0x0]))
(use (const_int 0 [0x0]))
(clobber (reg:SI 65 lr))
]) 457 {*call_nonlocal_sysvsi} (expr_list:REG_NORETURN (const_int 0 [0x0])
(expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil)))
(nil))
;; End of basic block 9 -> ()
;; lr out 1 [1] 67 [ap] 113 [sfp]
;; live out 1 [1] 67 [ap] 113 [sfp]
;; rd out (39)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 184, 186, 187
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 0 uid 49
;; reg 1 { d2(bb 0 insn -1) }
(barrier:HI 50 49 51)
;; Start of basic block ( 8) -> 10
;; bb 10 artificial_defs: { }
;; bb 10 artificial_uses: { u58(1){ d2(bb 0 insn -1) }u59(31){ d40(bb 0 insn -1) }u60(67){ d84(bb 0 insn -1) }u61(113){ d163(bb 0 insn -1) }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def 3 [3]
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen 3 [3]
;; live kill
;; rd in (39)
2, 9, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 184, 186, 187
;; rd gen (1)
5
;; rd kill (5)
5, 6, 7, 8, 9
;; DU chains for insn luid 0 uid 57
;; reg 3 { u62(bb 10 insn 63) u64(bb 1 insn -1) }
;; Pred edge 8 [100.0%]
(code_label:HI 51 50 52 10 11 "" [1 uses])
(note:HI 52 51 57 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn:HI 57 52 63 10 sms-6.c:38 (set (reg/i:SI 3 3)
(const_int 0 [0x0])) 334 {*movsi_internal1} (nil))
(insn:HI 63 57 0 10 sms-6.c:38 (use (reg/i:SI 3 3)) -1 (nil))
;; End of basic block 10 -> ( 1)
;; lr out 1 [1] 3 [3] 31 [31] 67 [ap] 113 [sfp]
;; live out 1 [1] 3 [3] 31 [31] 67 [ap] 113 [sfp]
;; rd out (39)
2, 5, 13, 17, 20, 23, 26, 29, 32, 35, 40, 45, 48, 51, 54, 57, 60, 63, 66, 84, 163, 164, 167, 168, 170, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 184, 186, 187
;; UD chains for artificial uses
;; reg 1 { d2(bb 0 insn -1) }
;; reg 31 { d40(bb 0 insn -1) }
;; reg 67 { d84(bb 0 insn -1) }
;; reg 113 { d163(bb 0 insn -1) }
;; UD chains for insn luid 1 uid 63
;; reg 3 { d5(bb 10 insn 57) }
;; Succ edge EXIT [100.0%] (fallthru)
starting the processing of deferred insns
ending the processing of deferred insns
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Solve transitive closure issue in modulo scheduling
2009-01-30 16:17 Solve transitive closure issue in modulo scheduling Bingfeng Mei
2009-02-01 23:18 ` Ayal Zaks
@ 2009-02-07 17:20 ` Daniel Berlin
1 sibling, 0 replies; 10+ messages in thread
From: Daniel Berlin @ 2009-02-07 17:20 UTC (permalink / raw)
To: Bingfeng Mei; +Cc: gcc, zaks, Adrian Ashley
On Fri, Jan 30, 2009 at 7:44 AM, Bingfeng Mei <bmei@broadcom.com> wrote:
> Hello,
> I try to make modulo scheduling work more efficiently for our VLIW target. I found one serious issue that prevents current SMS algorithm from achieving high IPC is so-called "transitive closure" problem, where scheduling window is only calculated using direct predecessors and successors. Because SMS is not an iterative algorithm, this may cause failures in finding a valid schedule. Without splitting rows, some simple loops just cannot be scheduled not matter how big the II is. With splitting rows, schedule can be found, but only at bigger II. GCC wiki (http://gcc.gnu.org/wiki/SwingModuloScheduling) lists this as a TODO. Is there any work going on about this issue (the last wiki update was one year ago)? If no one is working on it, I plan to do it. My idea is to use the MinDist algorithm described in B. Rau's classic paper "iterative modulo scheduling" (http://www.hpl.hp.com/techreports/94/HPL-94-115.html). The same algorithm can also be used to compute better RecMII. The biggest concern is complexity of computing MinDist matrix, which is O(N^3). N is number of nodes in the loop. I remember somewhere GCC coding guide says "never write quadratic algorithm" :-) Is this an absolute requirement?
It's not an absolute requirement, just a general guideline.
We have plenty of quadratic and worse algorithms, and we'd rather see
less of them :)
Obviously, when it comes to things requiring transitive closure, you
can't really do better.
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: Solve transitive closure issue in modulo scheduling
2009-02-05 10:45 ` Bingfeng Mei
@ 2009-02-17 12:03 ` Ayal Zaks
2009-03-13 6:43 ` [PATCH] SMS - Pass the actual schedulable rows to compute_split_row Revital1 Eres
2009-06-22 14:10 ` Unnecessary regmoves in modulo scheduler? Bingfeng Mei
0 siblings, 2 replies; 10+ messages in thread
From: Ayal Zaks @ 2009-02-17 12:03 UTC (permalink / raw)
To: Bingfeng Mei; +Cc: Revital1 Eres, Adrian Ashley, gcc
"Bingfeng Mei" <bmei@broadcom.com> wrote on 05/02/2009 12:45:20:
> Ayal,
> OOPs, your mail skipped my inbox and I missed it for several days.
>
I'm chasing after my mail as well..
> Using testsuite/gcc.dg/sms-6.c as an example and compiling it for
PowerPC,
> node 18 (see attachment) is in a SCC and cannot be scheduled until
spliting
> twice. The MII = 20 and the schedule can only be found at II = 24.
Yes, I see. This example raises a couple of issues:
o The first row split (from II=20 to II=21) is miscalculated; it should be
row 20=0 instead of 19. Splitting row 19 cannot help schedule node 18, and
indeed we immediately split another row. We're now checking a small patch
to fix this, which should save one cycle of II in the above example.
o The swinging scheduling procedure tends to create sets of densly
scheduled instructions with holes between them. For example, the set of
nodes 3, 7, 11, 15 first scheduled adjacently before (without leaving room
for) node 18 (in cycles 6 (=26 mod 20), 25, 24, 23 respectively). So it may
be possible to delete some empty row from such a hole (suffices to check a
single row from each hole), after we insert an empty row to accommodate an
instruction, thereby maintaining the II. This should save at-least one
additional cycle of II in the above example.
o Transitive closure can indeed prevent the construction of infeasible
partial schedules. Note that you'd be better off with a dense incidence
representation for the DDG, as it will become a complete graph. The
transitive DDG could be pruned according to the scheduling order, as we're
only interested in adding edge u -> v if there is some w on a path u ~> w
~> v where w follows both u and v in the to-be-scheduled order; but for
that you probably need to have transitive edges u -> w and w -> v ...
Plus, leaving a single cycle for w to be scheduled between u and v may not
be enough, as other instructions or conflicts may prevent w from eventually
being scheduled in this cycle. So the split (&remove) row mechanism may
still be useful.
o Another preventive (rather than corrective) action can be to prioritorize
register dependent nodes over memory dependent ones. Note that in the
example above, the 4 predecessors (7,11,15,18) of node 3 are equally
critical, and we're missing some tie-breaking criteria. It may be better to
prioritize node 18 due to its register dependence (the general motivation
being that near-by nodes imply shorter register live-ranges) over the other
nodes of output memory dependence. It's not easy however to extend the
current infrastructure to consider such criteria.
> On our 2-
> issue VLIW, the MII=10 and the valid schedule can only be found at II =
14. It
> is not great since we want to maximize performance.
>
> I had experience (in development of another compiler) on this issue by
> constructing the MinDist matrix and using it to calculate schedule window
for
> each instruction. However, speed was not a real concern then. Do you know
> better algorithm (better than O(N^3))?
No, I don't. As mentioned above, we might be able to save something by not
calculating the complete closure.
> Or do you think it is not so crtical
> here? After all, not many loops are candidates for software pipelining.
Thanks.
>
I would suggest to check the actual compile-time and memory usage, and try
to reduce them later if needed. Modulo-scheduling is not a compile-time
cheap optimization in general.
Ayal.
> Cheers,
> Bingfeng
>
> > -----Original Message-----
> > From: gcc-owner@gcc.gnu.org [mailto:gcc-owner@gcc.gnu.org] On
> > Behalf Of Ayal Zaks
> > Sent: 01 February 2009 23:18
> > To: Bingfeng Mei
> > Cc: Adrian Ashley; gcc@gcc.gnu.org
> > Subject: Re: Solve transitive closure issue in modulo scheduling
> >
> > "Bingfeng Mei" <bmei@broadcom.com> wrote on 30/01/2009 14:44:01:
> >
> > > Hello,
> > > I try to make modulo scheduling work more efficiently for our VLIW
> > target. I
> > > found one serious issue that prevents current SMS algorithm from
> > achieving
> > > high IPC is so-called "transitive closure" problem, where scheduling
> > window is
> > > only calculated using direct predecessors and successors.
> > Because SMS is
> > not
> > > an iterative algorithm, this may cause failures in finding a valid
> > schedule.
> >
> > Agreed.
> >
> > > Without splitting rows, some simple loops just cannot be
> > scheduled not
> > matter
> > > how big the II is. With splitting rows, schedule can be
> > found, but only
> > at
> > > bigger II.
> >
> > It may happen that even splitting rows will not help, e.g. when we
> > repeatedly end up with a node having negative sched window.
> >
> > > GCC wiki (http://gcc.gnu.org/wiki/SwingModuloScheduling) lists this
> > > as a TODO. Is there any work going on about this issue
> >
> > No, not to my knowledge. We had some testcase where this
> > showed up, hence
> > its appearance in the TODO, but afaicr some change caused it
> > to disappear.
> >
> > > (the last wiki update
> > > was one year ago)? If no one is working on it, I plan to do
> > it. My idea
> > is to
> > > use the MinDist algorithm described in B. Rau's classic
> > paper "iterative
> > > modulo
> > scheduling"
> > (>http://www.hpl.hp.com/techreports/94/HPL-94-115.html). The
> > > same algorithm can also be used to compute better RecMII.
> > The biggest
> > concern
> > > is complexity of computing MinDist matrix, which is O(N^3).
> > N is number
> > of
> > > nodes in the loop. I remember somewhere GCC coding guide says "never
> > write
> > > quadratic algorithm" :-) Is this an absolute requirement?
> > If yes, I will
> > keep
> > > it as our target-specific code (we are less concerned about
> > compilation
> > time).
> > > Otherwise, I will try to make it more generic to see if it
> > can make into
> > > mainline in 4.5. Any comments?
> > >
> >
> > The problem appears only when the DDG is cyclic, and for
> > every cycle in the
> > DDG, the problem may arise when trying to schedule the last
> > node of the
> > cycle, which has both predecessors and successors already
> > scheduled. So you
> > might try to connect only each such predecessor to every such
> > successor
> > with a transitive arc, to ensure that this last node will
> > have a non-empty
> > scheduling window. But this might not suffice; you may
> > eventually need to
> > wire (nearly) every pair of nodes in the strongly connected
> > component. If
> > this happens, you'd be better off with a dense graph representation
> > (incidence matrix) than the current sparse one (adjaceny lists).
> >
> > An example would help see things more clearly. If you have a
> > (small :) DDG
> > demonstrating the need for transitive arcs, I'd be happy to
> > have a look and
> > advise what should be done.
> >
> > Ayal.
> >
> > > Cheers,
> > > Bingfeng Mei
> > >
> > > Broadcom UK
> > >
> > >
> >
> >
> > [attachment "sms-6.c.169r.sms" deleted by Ayal Zaks/Haifa/IBM]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] SMS - Pass the actual schedulable rows to compute_split_row
2009-02-17 12:03 ` Ayal Zaks
@ 2009-03-13 6:43 ` Revital1 Eres
2009-06-22 14:10 ` Unnecessary regmoves in modulo scheduler? Bingfeng Mei
1 sibling, 0 replies; 10+ messages in thread
From: Revital1 Eres @ 2009-03-13 6:43 UTC (permalink / raw)
To: Ayal Zaks; +Cc: Adrian Ashley, Bingfeng Mei, gcc, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 943 bytes --]
Hello,
> > Using testsuite/gcc.dg/sms-6.c as an example and compiling it for
> PowerPC,
> > node 18 (see attachment) is in a SCC and cannot be scheduled until
> spliting
> > twice. The MII = 20 and the schedule can only be found at II = 24.
>
> Yes, I see. This example raises a couple of issues:
>
> o The first row split (from II=20 to II=21) is miscalculated; it should
be
> row 20=0 instead of 19. Splitting row 19 cannot help schedule node 18,
and
> indeed we immediately split another row. We're now checking a small patch
> to fix this, which should save one cycle of II in the above example.
Here is the patch, on behalf of Ayal.
Passed bootstrap + regtest with SMS flags on ppc64 and bootstrap +
regtest x86.
I'll commit it later today to trunk if that's OK.
Thanks,
Revital
* modulo-sched.c (sms_schedule_by_order): Pass the actual
schedulable rows to compute_split_row.
(See attached file: patch_sms_12_3.txt)
[-- Attachment #2: patch_sms_12_3.txt --]
[-- Type: text/plain, Size: 821 bytes --]
Index: modulo-sched.c
===================================================================
--- modulo-sched.c (revision 144739)
+++ modulo-sched.c (working copy)
@@ -1833,10 +1833,10 @@ sms_schedule_by_order (ddg_ptr g, int mi
num_splits++;
if (step == 1)
- split_row = compute_split_row (sched_nodes, start, end,
+ split_row = compute_split_row (sched_nodes, start, end - 1,
ps->ii, u_node);
else
- split_row = compute_split_row (sched_nodes, end, start,
+ split_row = compute_split_row (sched_nodes, end + 1, start,
ps->ii, u_node);
ps_insert_empty_row (ps, split_row, sched_nodes);
^ permalink raw reply [flat|nested] 10+ messages in thread
* Unnecessary regmoves in modulo scheduler?
2009-02-17 12:03 ` Ayal Zaks
2009-03-13 6:43 ` [PATCH] SMS - Pass the actual schedulable rows to compute_split_row Revital1 Eres
@ 2009-06-22 14:10 ` Bingfeng Mei
2009-06-23 13:41 ` Revital1 Eres
1 sibling, 1 reply; 10+ messages in thread
From: Bingfeng Mei @ 2009-06-22 14:10 UTC (permalink / raw)
To: Ayal Zaks; +Cc: Revital1 Eres, gcc
Hello, Ayal,
It may be a stupid a question :-). After reading the modulo scheduling code in GCC,
I have a question about necessity of generating reg moves. The reg move is supposed
to break register lifetime > II in absence of rotating register file. However,
in current GCC implementation, it seems unnecessary since extensive dependencies are
drawn between nodes in GCC.
Examining the DDG generated (a DDG based on sms-6.c is appended at the end of the mail),
I found a true register dependency is always accompanied with a cross-iteration
anti dependency. This should guarantee the true dependence cannot have lifetime
longer than II.
A --> B true dep (e.g., insn 36 -> insn 38 in the DDG)
B --> A anti dep with distance = 1 (e.g., insn 38 -> insn 36 in the DDG)
The second dependdency should lead to : Sched_Time(A) + II >(=) Sched_Time(B)
which means Sched_Time(B) - Sched_Time(A) <(=) II and no need for reg move.
Similarly, an anti register dependency is always accompanied with a cross-iteration
true dependency.
A --> B anti dep (e.g., insn 36 -> insn 53 in the DDG)
B --> A true dep with distance = 1 (e.g., insn 53 -> insn 36 in the DDG)
We can reach similar conclusion.
I wonder what other scenario would require to generate reg moves. Am I missing
some obvious points? Thanks in advance.
Cheers,
Bingfeng Mei
Broadcom UK
DDG from sms-6.c
SMS loop num: 1, file: sms-6.c, line: 9
Node num: 0
(insn 36 35 37 3 sms-6.c:11 (set (reg:SI 113)
(mem:SI (reg:SI 108 [ ivtmp.44 ]) [4 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [36 -(A,0,0)-> 53] [36 -(T,6,0)-> 38]
IN ARCS: [38 -(A,0,1)-> 36] [53 -(T,1,1)-> 36]
Node num: 1
(insn 37 36 38 3 sms-6.c:11 (set (reg:SI 114)
(mem:SI (reg:SI 109 [ ivtmp.42 ]) [5 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [37 -(A,0,0)-> 52] [37 -(T,6,0)-> 38]
IN ARCS: [38 -(A,0,1)-> 37] [52 -(T,1,1)-> 37]
Node num: 2
(insn 38 37 39 3 sms-6.c:11 (set (reg:SI 115)
(mult:SI (reg:SI 113)
(reg:SI 114))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 114)
(expr_list:REG_DEAD (reg:SI 113)
(nil))))
OUT ARCS: [38 -(A,0,1)-> 37] [38 -(A,0,1)-> 36] [38 -(T,8,0)-> 39]
IN ARCS: [39 -(A,0,1)-> 38] [36 -(T,6,0)-> 38] [37 -(T,6,0)-> 38]
Node num: 3
(insn 39 38 40 3 sms-6.c:11 (set (mem:SI (reg:SI 107 [ ivtmp.45 ]) [3 S4 A32])
(reg:SI 115)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 115)
(nil)))
OUT ARCS: [39 -(A,0,1)-> 38] [39 -(O,1,0)-> 69] [39 -(A,0,0)-> 54]
IN ARCS: [54 -(T,1,1)-> 39] [51 -(O,1,1)-> 39] [47 -(O,1,1)-> 39] [43 -(O,1,1)-> 39] [38 -(T,8,0)-> 39]
Node num: 4
(insn 40 39 41 3 sms-6.c:12 (set (reg:SI 116)
(mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
(const_int 4 [0x4])) [4 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [40 -(A,0,0)-> 53] [40 -(T,6,0)-> 42]
IN ARCS: [42 -(A,0,1)-> 40] [53 -(T,1,1)-> 40]
Node num: 5
(insn 41 40 42 3 sms-6.c:12 (set (reg:SI 117)
(mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
(const_int 4 [0x4])) [5 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [41 -(A,0,0)-> 52] [41 -(T,6,0)-> 42]
IN ARCS: [42 -(A,0,1)-> 41] [52 -(T,1,1)-> 41]
Node num: 6
(insn 42 41 43 3 sms-6.c:12 (set (reg:SI 118)
(mult:SI (reg:SI 116)
(reg:SI 117))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 117)
(expr_list:REG_DEAD (reg:SI 116)
(nil))))
OUT ARCS: [42 -(A,0,1)-> 41] [42 -(A,0,1)-> 40] [42 -(T,8,0)-> 43]
IN ARCS: [43 -(A,0,1)-> 42] [40 -(T,6,0)-> 42] [41 -(T,6,0)-> 42]
Node num: 7
(insn 43 42 44 3 sms-6.c:12 (set (mem:SI (plus:SI (reg:SI 107 [ ivtmp.45 ])
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 118)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 118)
(nil)))
OUT ARCS: [43 -(A,0,1)-> 42] [43 -(O,1,0)-> 69] [43 -(A,0,0)-> 54] [43 -(O,1,1)-> 39]
IN ARCS: [54 -(T,1,1)-> 43] [51 -(O,1,1)-> 43] [47 -(O,1,1)-> 43] [42 -(T,8,0)-> 43]
Node num: 8
(insn 44 43 45 3 sms-6.c:13 (set (reg:SI 119)
(mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
(const_int 8 [0x8])) [4 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [44 -(A,0,0)-> 53] [44 -(T,6,0)-> 46]
IN ARCS: [46 -(A,0,1)-> 44] [53 -(T,1,1)-> 44]
Node num: 9
(insn 45 44 46 3 sms-6.c:13 (set (reg:SI 120)
(mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
(const_int 8 [0x8])) [5 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [45 -(A,0,0)-> 52] [45 -(T,6,0)-> 46]
IN ARCS: [46 -(A,0,1)-> 45] [52 -(T,1,1)-> 45]
Node num: 10
(insn 46 45 47 3 sms-6.c:13 (set (reg:SI 121)
(mult:SI (reg:SI 119)
(reg:SI 120))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 120)
(expr_list:REG_DEAD (reg:SI 119)
(nil))))
OUT ARCS: [46 -(A,0,1)-> 45] [46 -(A,0,1)-> 44] [46 -(T,8,0)-> 47]
IN ARCS: [47 -(A,0,1)-> 46] [44 -(T,6,0)-> 46] [45 -(T,6,0)-> 46]
Node num: 11
(insn 47 46 48 3 sms-6.c:13 (set (mem:SI (plus:SI (reg:SI 107 [ ivtmp.45 ])
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 121)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 121)
(nil)))
OUT ARCS: [47 -(A,0,1)-> 46] [47 -(O,1,0)-> 69] [47 -(A,0,0)-> 54] [47 -(O,1,1)-> 43] [47 -(O,1,1)-> 39]
IN ARCS: [54 -(T,1,1)-> 47] [51 -(O,1,1)-> 47] [46 -(T,8,0)-> 47]
Node num: 12
(insn 48 47 49 3 sms-6.c:14 (set (reg:SI 122)
(mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
(const_int 12 [0xc])) [4 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [48 -(A,0,0)-> 53] [48 -(T,6,0)-> 50]
IN ARCS: [50 -(A,0,1)-> 48] [53 -(T,1,1)-> 48]
Node num: 13
(insn 49 48 50 3 sms-6.c:14 (set (reg:SI 123)
(mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
(const_int 12 [0xc])) [5 S4 A32])) 184 {*movwsi} (nil))
OUT ARCS: [49 -(A,0,0)-> 52] [49 -(T,6,0)-> 50]
IN ARCS: [50 -(A,0,1)-> 49] [52 -(T,1,1)-> 49]
Node num: 14
(insn 50 49 51 3 sms-6.c:14 (set (reg:SI 124)
(mult:SI (reg:SI 122)
(reg:SI 123))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 123)
(expr_list:REG_DEAD (reg:SI 122)
(nil))))
OUT ARCS: [50 -(A,0,1)-> 49] [50 -(A,0,1)-> 48] [50 -(T,8,0)-> 51]
IN ARCS: [51 -(A,0,1)-> 50] [48 -(T,6,0)-> 50] [49 -(T,6,0)-> 50]
Node num: 15
(insn 51 50 52 3 sms-6.c:14 (set (mem:SI (plus:SI (reg:SI 107 [ ivtmp.45 ])
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 124)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 124)
(nil)))
OUT ARCS: [51 -(A,0,1)-> 50] [51 -(O,1,0)-> 69] [51 -(A,0,0)-> 54] [51 -(O,1,1)-> 47] [51 -(O,1,1)-> 43] [51 -(O,1,1)-> 39]
IN ARCS: [54 -(T,1,1)-> 51] [50 -(T,8,0)-> 51]
Node num: 16
(insn 52 51 53 3 sms-6.c:14 (set (reg:SI 109 [ ivtmp.42 ])
(plus:SI (reg:SI 109 [ ivtmp.42 ])
(const_int 16 [0x10]))) 220 {addsi3} (nil))
OUT ARCS: [52 -(T,1,1)-> 37] [52 -(T,1,1)-> 41] [52 -(T,1,1)-> 45] [52 -(T,1,1)-> 49] [52 -(T,1,1)-> 52]
IN ARCS: [52 -(T,1,1)-> 52] [49 -(A,0,0)-> 52] [45 -(A,0,0)-> 52] [41 -(A,0,0)-> 52] [37 -(A,0,0)-> 52]
Node num: 17
(insn 53 52 54 3 sms-6.c:14 (set (reg:SI 108 [ ivtmp.44 ])
(plus:SI (reg:SI 108 [ ivtmp.44 ])
(const_int 16 [0x10]))) 220 {addsi3} (nil))
OUT ARCS: [53 -(T,1,1)-> 36] [53 -(T,1,1)-> 40] [53 -(T,1,1)-> 44] [53 -(T,1,1)-> 48] [53 -(T,1,1)-> 53]
IN ARCS: [53 -(T,1,1)-> 53] [48 -(A,0,0)-> 53] [44 -(A,0,0)-> 53] [40 -(A,0,0)-> 53] [36 -(A,0,0)-> 53]
Node num: 18
(insn 54 53 69 3 sms-6.c:14 (set (reg:SI 107 [ ivtmp.45 ])
(plus:SI (reg:SI 107 [ ivtmp.45 ])
(const_int 16 [0x10]))) 220 {addsi3} (nil))
OUT ARCS: [54 -(T,1,1)-> 39] [54 -(T,1,1)-> 43] [54 -(T,1,1)-> 47] [54 -(T,1,1)-> 51] [54 -(T,1,1)-> 54]
IN ARCS: [54 -(T,1,1)-> 54] [51 -(A,0,0)-> 54] [47 -(A,0,0)-> 54] [43 -(A,0,0)-> 54] [39 -(A,0,0)-> 54]
Node num: 19
(jump_insn 69 54 65 3 sms-6.c:9 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 126)
(const_int 1 [0x1]))
(label_ref:SI 55)
(pc)))
(set (reg:SI 126)
(plus:SI (reg:SI 126)
(const_int -1 [0xffffffff])))
(unspec [
(const_int 0 [0x0])
] 98)
(clobber (reg:BI 70 p6))
(clobber (scratch:SI))
(clobber (scratch:SI))
]) 1047 {fp_loop_endsi} (expr_list:REG_UNUSED (reg:BI 70 p6)
(expr_list:REG_BR_PROB (const_int 9600 [0x2580])
(nil))))
OUT ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69]
IN ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69] [51 -(O,1,0)-> 69] [47 -(O,1,0)-> 69] [43 -(O,1,0)-> 69] [39 -(O,1,0)-> 69]
sms-6.c 9 (file, line)
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Unnecessary regmoves in modulo scheduler?
2009-06-22 14:10 ` Unnecessary regmoves in modulo scheduler? Bingfeng Mei
@ 2009-06-23 13:41 ` Revital1 Eres
2009-06-23 13:48 ` Bingfeng Mei
0 siblings, 1 reply; 10+ messages in thread
From: Revital1 Eres @ 2009-06-23 13:41 UTC (permalink / raw)
To: Bingfeng Mei; +Cc: Ayal Zaks, gcc
Hello Bingfeng,
> I found a true register dependency is always accompanied with a
cross-iteration
> anti dependency.
When -fmodulo-sched-allow-regmoves flag is set some anti-deps edges are not
created.
Please see add_cross_iteration_register_deps () function in ddg.c.
HTH,
Revital
This should guarantee the true dependence cannot have lifetime
> longer than II.
>
> A --> B true dep (e.g., insn 36 -> insn 38 in the
DDG)
> B --> A anti dep with distance = 1 (e.g., insn 38 -> insn 36 in the
DDG)
>
> The second dependdency should lead to : Sched_Time(A) + II >(=)
Sched_Time(B)
> which means Sched_Time(B) - Sched_Time(A) <(=) II and no need for reg
move.
>
> Similarly, an anti register dependency is always accompanied with a
cross-iteration
> true dependency.
>
> A --> B anti dep (e.g., insn 36 -> insn 53 in the
DDG)
> B --> A true dep with distance = 1 (e.g., insn 53 -> insn 36 in the
DDG)
> We can reach similar conclusion.
>
> I wonder what other scenario would require to generate reg moves. Am I
missing
> some obvious points? Thanks in advance.
>
>
> Cheers,
> Bingfeng Mei
>
> Broadcom UK
>
>
> DDG from sms-6.c
> SMS loop num: 1, file: sms-6.c, line: 9
> Node num: 0
> (insn 36 35 37 3 sms-6.c:11 (set (reg:SI 113)
> (mem:SI (reg:SI 108 [ ivtmp.44 ]) [4 S4 A32])) 184 {*movwsi}
(nil))
> OUT ARCS: [36 -(A,0,0)-> 53] [36 -(T,6,0)-> 38]
> IN ARCS: [38 -(A,0,1)-> 36] [53 -(T,1,1)-> 36]
> Node num: 1
> (insn 37 36 38 3 sms-6.c:11 (set (reg:SI 114)
> (mem:SI (reg:SI 109 [ ivtmp.42 ]) [5 S4 A32])) 184 {*movwsi}
(nil))
> OUT ARCS: [37 -(A,0,0)-> 52] [37 -(T,6,0)-> 38]
> IN ARCS: [38 -(A,0,1)-> 37] [52 -(T,1,1)-> 37]
> Node num: 2
> (insn 38 37 39 3 sms-6.c:11 (set (reg:SI 115)
> (mult:SI (reg:SI 113)
> (reg:SI 114))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 114)
> (expr_list:REG_DEAD (reg:SI 113)
> (nil))))
> OUT ARCS: [38 -(A,0,1)-> 37] [38 -(A,0,1)-> 36] [38 -(T,8,0)-> 39]
> IN ARCS: [39 -(A,0,1)-> 38] [36 -(T,6,0)-> 38] [37 -(T,6,0)-> 38]
> Node num: 3
> (insn 39 38 40 3 sms-6.c:11 (set (mem:SI (reg:SI 107 [ ivtmp.45 ]) [3 S4
A32])
> (reg:SI 115)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 115)
> (nil)))
> OUT ARCS: [39 -(A,0,1)-> 38] [39 -(O,1,0)-> 69] [39 -(A,0,0)-> 54]
> IN ARCS: [54 -(T,1,1)-> 39] [51 -(O,1,1)-> 39] [47 -(O,1,1)-> 39] [43
-(O,
> 1,1)-> 39] [38 -(T,8,0)-> 39]
> Node num: 4
> (insn 40 39 41 3 sms-6.c:12 (set (reg:SI 116)
> (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> (const_int 4 [0x4])) [4 S4 A32])) 184 {*movwsi} (nil))
> OUT ARCS: [40 -(A,0,0)-> 53] [40 -(T,6,0)-> 42]
> IN ARCS: [42 -(A,0,1)-> 40] [53 -(T,1,1)-> 40]
> Node num: 5
> (insn 41 40 42 3 sms-6.c:12 (set (reg:SI 117)
> (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> (const_int 4 [0x4])) [5 S4 A32])) 184 {*movwsi} (nil))
> OUT ARCS: [41 -(A,0,0)-> 52] [41 -(T,6,0)-> 42]
> IN ARCS: [42 -(A,0,1)-> 41] [52 -(T,1,1)-> 41]
> Node num: 6
> (insn 42 41 43 3 sms-6.c:12 (set (reg:SI 118)
> (mult:SI (reg:SI 116)
> (reg:SI 117))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 117)
> (expr_list:REG_DEAD (reg:SI 116)
> (nil))))
> OUT ARCS: [42 -(A,0,1)-> 41] [42 -(A,0,1)-> 40] [42 -(T,8,0)-> 43]
> IN ARCS: [43 -(A,0,1)-> 42] [40 -(T,6,0)-> 42] [41 -(T,6,0)-> 42]
> Node num: 7
> (insn 43 42 44 3 sms-6.c:12 (set (mem:SI (plus:SI (reg:SI 107
[ ivtmp.45 ])
> (const_int 4 [0x4])) [3 S4 A32])
> (reg:SI 118)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 118)
> (nil)))
> OUT ARCS: [43 -(A,0,1)-> 42] [43 -(O,1,0)-> 69] [43 -(A,0,0)-> 54]
[43 -
> (O,1,1)-> 39]
> IN ARCS: [54 -(T,1,1)-> 43] [51 -(O,1,1)-> 43] [47 -(O,1,1)-> 43] [42
-(T,
> 8,0)-> 43]
> Node num: 8
> (insn 44 43 45 3 sms-6.c:13 (set (reg:SI 119)
> (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> (const_int 8 [0x8])) [4 S4 A32])) 184 {*movwsi} (nil))
> OUT ARCS: [44 -(A,0,0)-> 53] [44 -(T,6,0)-> 46]
> IN ARCS: [46 -(A,0,1)-> 44] [53 -(T,1,1)-> 44]
> Node num: 9
> (insn 45 44 46 3 sms-6.c:13 (set (reg:SI 120)
> (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> (const_int 8 [0x8])) [5 S4 A32])) 184 {*movwsi} (nil))
> OUT ARCS: [45 -(A,0,0)-> 52] [45 -(T,6,0)-> 46]
> IN ARCS: [46 -(A,0,1)-> 45] [52 -(T,1,1)-> 45]
> Node num: 10
> (insn 46 45 47 3 sms-6.c:13 (set (reg:SI 121)
> (mult:SI (reg:SI 119)
> (reg:SI 120))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 120)
> (expr_list:REG_DEAD (reg:SI 119)
> (nil))))
> OUT ARCS: [46 -(A,0,1)-> 45] [46 -(A,0,1)-> 44] [46 -(T,8,0)-> 47]
> IN ARCS: [47 -(A,0,1)-> 46] [44 -(T,6,0)-> 46] [45 -(T,6,0)-> 46]
> Node num: 11
> (insn 47 46 48 3 sms-6.c:13 (set (mem:SI (plus:SI (reg:SI 107
[ ivtmp.45 ])
> (const_int 8 [0x8])) [3 S4 A32])
> (reg:SI 121)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 121)
> (nil)))
> OUT ARCS: [47 -(A,0,1)-> 46] [47 -(O,1,0)-> 69] [47 -(A,0,0)-> 54]
[47 -
> (O,1,1)-> 43] [47 -(O,1,1)-> 39]
> IN ARCS: [54 -(T,1,1)-> 47] [51 -(O,1,1)-> 47] [46 -(T,8,0)-> 47]
> Node num: 12
> (insn 48 47 49 3 sms-6.c:14 (set (reg:SI 122)
> (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> (const_int 12 [0xc])) [4 S4 A32])) 184 {*movwsi} (nil))
> OUT ARCS: [48 -(A,0,0)-> 53] [48 -(T,6,0)-> 50]
> IN ARCS: [50 -(A,0,1)-> 48] [53 -(T,1,1)-> 48]
> Node num: 13
> (insn 49 48 50 3 sms-6.c:14 (set (reg:SI 123)
> (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> (const_int 12 [0xc])) [5 S4 A32])) 184 {*movwsi} (nil))
> OUT ARCS: [49 -(A,0,0)-> 52] [49 -(T,6,0)-> 50]
> IN ARCS: [50 -(A,0,1)-> 49] [52 -(T,1,1)-> 49]
> Node num: 14
> (insn 50 49 51 3 sms-6.c:14 (set (reg:SI 124)
> (mult:SI (reg:SI 122)
> (reg:SI 123))) 262 {mulsi3} (expr_list:REG_DEAD (reg:SI 123)
> (expr_list:REG_DEAD (reg:SI 122)
> (nil))))
> OUT ARCS: [50 -(A,0,1)-> 49] [50 -(A,0,1)-> 48] [50 -(T,8,0)-> 51]
> IN ARCS: [51 -(A,0,1)-> 50] [48 -(T,6,0)-> 50] [49 -(T,6,0)-> 50]
> Node num: 15
> (insn 51 50 52 3 sms-6.c:14 (set (mem:SI (plus:SI (reg:SI 107
[ ivtmp.45 ])
> (const_int 12 [0xc])) [3 S4 A32])
> (reg:SI 124)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 124)
> (nil)))
> OUT ARCS: [51 -(A,0,1)-> 50] [51 -(O,1,0)-> 69] [51 -(A,0,0)-> 54]
[51 -
> (O,1,1)-> 47] [51 -(O,1,1)-> 43] [51 -(O,1,1)-> 39]
> IN ARCS: [54 -(T,1,1)-> 51] [50 -(T,8,0)-> 51]
> Node num: 16
> (insn 52 51 53 3 sms-6.c:14 (set (reg:SI 109 [ ivtmp.42 ])
> (plus:SI (reg:SI 109 [ ivtmp.42 ])
> (const_int 16 [0x10]))) 220 {addsi3} (nil))
> OUT ARCS: [52 -(T,1,1)-> 37] [52 -(T,1,1)-> 41] [52 -(T,1,1)-> 45]
[52 -
> (T,1,1)-> 49] [52 -(T,1,1)-> 52]
> IN ARCS: [52 -(T,1,1)-> 52] [49 -(A,0,0)-> 52] [45 -(A,0,0)-> 52] [41
-(A,
> 0,0)-> 52] [37 -(A,0,0)-> 52]
> Node num: 17
> (insn 53 52 54 3 sms-6.c:14 (set (reg:SI 108 [ ivtmp.44 ])
> (plus:SI (reg:SI 108 [ ivtmp.44 ])
> (const_int 16 [0x10]))) 220 {addsi3} (nil))
> OUT ARCS: [53 -(T,1,1)-> 36] [53 -(T,1,1)-> 40] [53 -(T,1,1)-> 44]
[53 -
> (T,1,1)-> 48] [53 -(T,1,1)-> 53]
> IN ARCS: [53 -(T,1,1)-> 53] [48 -(A,0,0)-> 53] [44 -(A,0,0)-> 53] [40
-(A,
> 0,0)-> 53] [36 -(A,0,0)-> 53]
> Node num: 18
> (insn 54 53 69 3 sms-6.c:14 (set (reg:SI 107 [ ivtmp.45 ])
> (plus:SI (reg:SI 107 [ ivtmp.45 ])
> (const_int 16 [0x10]))) 220 {addsi3} (nil))
> OUT ARCS: [54 -(T,1,1)-> 39] [54 -(T,1,1)-> 43] [54 -(T,1,1)-> 47]
[54 -
> (T,1,1)-> 51] [54 -(T,1,1)-> 54]
> IN ARCS: [54 -(T,1,1)-> 54] [51 -(A,0,0)-> 54] [47 -(A,0,0)-> 54] [43
-(A,
> 0,0)-> 54] [39 -(A,0,0)-> 54]
> Node num: 19
> (jump_insn 69 54 65 3 sms-6.c:9 (parallel [
> (set (pc)
> (if_then_else (ne (reg:SI 126)
> (const_int 1 [0x1]))
> (label_ref:SI 55)
> (pc)))
> (set (reg:SI 126)
> (plus:SI (reg:SI 126)
> (const_int -1 [0xffffffff])))
> (unspec [
> (const_int 0 [0x0])
> ] 98)
> (clobber (reg:BI 70 p6))
> (clobber (scratch:SI))
> (clobber (scratch:SI))
> ]) 1047 {fp_loop_endsi} (expr_list:REG_UNUSED (reg:BI 70 p6)
> (expr_list:REG_BR_PROB (const_int 9600 [0x2580])
> (nil))))
> OUT ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69]
> IN ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69] [51 -(O,1,0)-> 69] [47
-(O,
> 1,0)-> 69] [43 -(O,1,0)-> 69] [39 -(O,1,0)-> 69]
> sms-6.c 9 (file, line)
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: Unnecessary regmoves in modulo scheduler?
2009-06-23 13:41 ` Revital1 Eres
@ 2009-06-23 13:48 ` Bingfeng Mei
2009-06-23 13:56 ` Revital1 Eres
0 siblings, 1 reply; 10+ messages in thread
From: Bingfeng Mei @ 2009-06-23 13:48 UTC (permalink / raw)
To: Revital1 Eres; +Cc: Ayal Zaks, gcc
Thanks. I didn't notice the option. Which approach is generally better
according to your experience? Producing regmoves or more depedencies?
> -----Original Message-----
> From: Revital1 Eres [mailto:ERES@il.ibm.com]
> Sent: 23 June 2009 14:40
> To: Bingfeng Mei
> Cc: Ayal Zaks; gcc@gcc.gnu.org
> Subject: Re: Unnecessary regmoves in modulo scheduler?
>
> Hello Bingfeng,
>
> > I found a true register dependency is always accompanied with a
> cross-iteration
> > anti dependency.
>
> When -fmodulo-sched-allow-regmoves flag is set some anti-deps
> edges are not
> created.
> Please see add_cross_iteration_register_deps () function in ddg.c.
>
> HTH,
> Revital
>
> This should guarantee the true dependence cannot have lifetime
> > longer than II.
> >
> > A --> B true dep (e.g., insn 36 -> insn
> 38 in the
> DDG)
> > B --> A anti dep with distance = 1 (e.g., insn 38 ->
> insn 36 in the
> DDG)
> >
> > The second dependdency should lead to : Sched_Time(A) + II >(=)
> Sched_Time(B)
> > which means Sched_Time(B) - Sched_Time(A) <(=) II and no
> need for reg
> move.
> >
> > Similarly, an anti register dependency is always accompanied with a
> cross-iteration
> > true dependency.
> >
> > A --> B anti dep (e.g., insn 36 ->
> insn 53 in the
> DDG)
> > B --> A true dep with distance = 1 (e.g., insn 53 ->
> insn 36 in the
> DDG)
> > We can reach similar conclusion.
> >
> > I wonder what other scenario would require to generate reg
> moves. Am I
> missing
> > some obvious points? Thanks in advance.
> >
> >
> > Cheers,
> > Bingfeng Mei
> >
> > Broadcom UK
> >
> >
> > DDG from sms-6.c
> > SMS loop num: 1, file: sms-6.c, line: 9
> > Node num: 0
> > (insn 36 35 37 3 sms-6.c:11 (set (reg:SI 113)
> > (mem:SI (reg:SI 108 [ ivtmp.44 ]) [4 S4 A32])) 184 {*movwsi}
> (nil))
> > OUT ARCS: [36 -(A,0,0)-> 53] [36 -(T,6,0)-> 38]
> > IN ARCS: [38 -(A,0,1)-> 36] [53 -(T,1,1)-> 36]
> > Node num: 1
> > (insn 37 36 38 3 sms-6.c:11 (set (reg:SI 114)
> > (mem:SI (reg:SI 109 [ ivtmp.42 ]) [5 S4 A32])) 184 {*movwsi}
> (nil))
> > OUT ARCS: [37 -(A,0,0)-> 52] [37 -(T,6,0)-> 38]
> > IN ARCS: [38 -(A,0,1)-> 37] [52 -(T,1,1)-> 37]
> > Node num: 2
> > (insn 38 37 39 3 sms-6.c:11 (set (reg:SI 115)
> > (mult:SI (reg:SI 113)
> > (reg:SI 114))) 262 {mulsi3} (expr_list:REG_DEAD
> (reg:SI 114)
> > (expr_list:REG_DEAD (reg:SI 113)
> > (nil))))
> > OUT ARCS: [38 -(A,0,1)-> 37] [38 -(A,0,1)-> 36] [38
> -(T,8,0)-> 39]
> > IN ARCS: [39 -(A,0,1)-> 38] [36 -(T,6,0)-> 38] [37 -(T,6,0)-> 38]
> > Node num: 3
> > (insn 39 38 40 3 sms-6.c:11 (set (mem:SI (reg:SI 107 [
> ivtmp.45 ]) [3 S4
> A32])
> > (reg:SI 115)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 115)
> > (nil)))
> > OUT ARCS: [39 -(A,0,1)-> 38] [39 -(O,1,0)-> 69] [39
> -(A,0,0)-> 54]
> > IN ARCS: [54 -(T,1,1)-> 39] [51 -(O,1,1)-> 39] [47
> -(O,1,1)-> 39] [43
> -(O,
> > 1,1)-> 39] [38 -(T,8,0)-> 39]
> > Node num: 4
> > (insn 40 39 41 3 sms-6.c:12 (set (reg:SI 116)
> > (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > (const_int 4 [0x4])) [4 S4 A32])) 184
> {*movwsi} (nil))
> > OUT ARCS: [40 -(A,0,0)-> 53] [40 -(T,6,0)-> 42]
> > IN ARCS: [42 -(A,0,1)-> 40] [53 -(T,1,1)-> 40]
> > Node num: 5
> > (insn 41 40 42 3 sms-6.c:12 (set (reg:SI 117)
> > (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > (const_int 4 [0x4])) [5 S4 A32])) 184
> {*movwsi} (nil))
> > OUT ARCS: [41 -(A,0,0)-> 52] [41 -(T,6,0)-> 42]
> > IN ARCS: [42 -(A,0,1)-> 41] [52 -(T,1,1)-> 41]
> > Node num: 6
> > (insn 42 41 43 3 sms-6.c:12 (set (reg:SI 118)
> > (mult:SI (reg:SI 116)
> > (reg:SI 117))) 262 {mulsi3} (expr_list:REG_DEAD
> (reg:SI 117)
> > (expr_list:REG_DEAD (reg:SI 116)
> > (nil))))
> > OUT ARCS: [42 -(A,0,1)-> 41] [42 -(A,0,1)-> 40] [42
> -(T,8,0)-> 43]
> > IN ARCS: [43 -(A,0,1)-> 42] [40 -(T,6,0)-> 42] [41 -(T,6,0)-> 42]
> > Node num: 7
> > (insn 43 42 44 3 sms-6.c:12 (set (mem:SI (plus:SI (reg:SI 107
> [ ivtmp.45 ])
> > (const_int 4 [0x4])) [3 S4 A32])
> > (reg:SI 118)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 118)
> > (nil)))
> > OUT ARCS: [43 -(A,0,1)-> 42] [43 -(O,1,0)-> 69] [43
> -(A,0,0)-> 54]
> [43 -
> > (O,1,1)-> 39]
> > IN ARCS: [54 -(T,1,1)-> 43] [51 -(O,1,1)-> 43] [47
> -(O,1,1)-> 43] [42
> -(T,
> > 8,0)-> 43]
> > Node num: 8
> > (insn 44 43 45 3 sms-6.c:13 (set (reg:SI 119)
> > (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > (const_int 8 [0x8])) [4 S4 A32])) 184
> {*movwsi} (nil))
> > OUT ARCS: [44 -(A,0,0)-> 53] [44 -(T,6,0)-> 46]
> > IN ARCS: [46 -(A,0,1)-> 44] [53 -(T,1,1)-> 44]
> > Node num: 9
> > (insn 45 44 46 3 sms-6.c:13 (set (reg:SI 120)
> > (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > (const_int 8 [0x8])) [5 S4 A32])) 184
> {*movwsi} (nil))
> > OUT ARCS: [45 -(A,0,0)-> 52] [45 -(T,6,0)-> 46]
> > IN ARCS: [46 -(A,0,1)-> 45] [52 -(T,1,1)-> 45]
> > Node num: 10
> > (insn 46 45 47 3 sms-6.c:13 (set (reg:SI 121)
> > (mult:SI (reg:SI 119)
> > (reg:SI 120))) 262 {mulsi3} (expr_list:REG_DEAD
> (reg:SI 120)
> > (expr_list:REG_DEAD (reg:SI 119)
> > (nil))))
> > OUT ARCS: [46 -(A,0,1)-> 45] [46 -(A,0,1)-> 44] [46
> -(T,8,0)-> 47]
> > IN ARCS: [47 -(A,0,1)-> 46] [44 -(T,6,0)-> 46] [45 -(T,6,0)-> 46]
> > Node num: 11
> > (insn 47 46 48 3 sms-6.c:13 (set (mem:SI (plus:SI (reg:SI 107
> [ ivtmp.45 ])
> > (const_int 8 [0x8])) [3 S4 A32])
> > (reg:SI 121)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 121)
> > (nil)))
> > OUT ARCS: [47 -(A,0,1)-> 46] [47 -(O,1,0)-> 69] [47
> -(A,0,0)-> 54]
> [47 -
> > (O,1,1)-> 43] [47 -(O,1,1)-> 39]
> > IN ARCS: [54 -(T,1,1)-> 47] [51 -(O,1,1)-> 47] [46 -(T,8,0)-> 47]
> > Node num: 12
> > (insn 48 47 49 3 sms-6.c:14 (set (reg:SI 122)
> > (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > (const_int 12 [0xc])) [4 S4 A32])) 184
> {*movwsi} (nil))
> > OUT ARCS: [48 -(A,0,0)-> 53] [48 -(T,6,0)-> 50]
> > IN ARCS: [50 -(A,0,1)-> 48] [53 -(T,1,1)-> 48]
> > Node num: 13
> > (insn 49 48 50 3 sms-6.c:14 (set (reg:SI 123)
> > (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > (const_int 12 [0xc])) [5 S4 A32])) 184
> {*movwsi} (nil))
> > OUT ARCS: [49 -(A,0,0)-> 52] [49 -(T,6,0)-> 50]
> > IN ARCS: [50 -(A,0,1)-> 49] [52 -(T,1,1)-> 49]
> > Node num: 14
> > (insn 50 49 51 3 sms-6.c:14 (set (reg:SI 124)
> > (mult:SI (reg:SI 122)
> > (reg:SI 123))) 262 {mulsi3} (expr_list:REG_DEAD
> (reg:SI 123)
> > (expr_list:REG_DEAD (reg:SI 122)
> > (nil))))
> > OUT ARCS: [50 -(A,0,1)-> 49] [50 -(A,0,1)-> 48] [50
> -(T,8,0)-> 51]
> > IN ARCS: [51 -(A,0,1)-> 50] [48 -(T,6,0)-> 50] [49 -(T,6,0)-> 50]
> > Node num: 15
> > (insn 51 50 52 3 sms-6.c:14 (set (mem:SI (plus:SI (reg:SI 107
> [ ivtmp.45 ])
> > (const_int 12 [0xc])) [3 S4 A32])
> > (reg:SI 124)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 124)
> > (nil)))
> > OUT ARCS: [51 -(A,0,1)-> 50] [51 -(O,1,0)-> 69] [51
> -(A,0,0)-> 54]
> [51 -
> > (O,1,1)-> 47] [51 -(O,1,1)-> 43] [51 -(O,1,1)-> 39]
> > IN ARCS: [54 -(T,1,1)-> 51] [50 -(T,8,0)-> 51]
> > Node num: 16
> > (insn 52 51 53 3 sms-6.c:14 (set (reg:SI 109 [ ivtmp.42 ])
> > (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > (const_int 16 [0x10]))) 220 {addsi3} (nil))
> > OUT ARCS: [52 -(T,1,1)-> 37] [52 -(T,1,1)-> 41] [52
> -(T,1,1)-> 45]
> [52 -
> > (T,1,1)-> 49] [52 -(T,1,1)-> 52]
> > IN ARCS: [52 -(T,1,1)-> 52] [49 -(A,0,0)-> 52] [45
> -(A,0,0)-> 52] [41
> -(A,
> > 0,0)-> 52] [37 -(A,0,0)-> 52]
> > Node num: 17
> > (insn 53 52 54 3 sms-6.c:14 (set (reg:SI 108 [ ivtmp.44 ])
> > (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > (const_int 16 [0x10]))) 220 {addsi3} (nil))
> > OUT ARCS: [53 -(T,1,1)-> 36] [53 -(T,1,1)-> 40] [53
> -(T,1,1)-> 44]
> [53 -
> > (T,1,1)-> 48] [53 -(T,1,1)-> 53]
> > IN ARCS: [53 -(T,1,1)-> 53] [48 -(A,0,0)-> 53] [44
> -(A,0,0)-> 53] [40
> -(A,
> > 0,0)-> 53] [36 -(A,0,0)-> 53]
> > Node num: 18
> > (insn 54 53 69 3 sms-6.c:14 (set (reg:SI 107 [ ivtmp.45 ])
> > (plus:SI (reg:SI 107 [ ivtmp.45 ])
> > (const_int 16 [0x10]))) 220 {addsi3} (nil))
> > OUT ARCS: [54 -(T,1,1)-> 39] [54 -(T,1,1)-> 43] [54
> -(T,1,1)-> 47]
> [54 -
> > (T,1,1)-> 51] [54 -(T,1,1)-> 54]
> > IN ARCS: [54 -(T,1,1)-> 54] [51 -(A,0,0)-> 54] [47
> -(A,0,0)-> 54] [43
> -(A,
> > 0,0)-> 54] [39 -(A,0,0)-> 54]
> > Node num: 19
> > (jump_insn 69 54 65 3 sms-6.c:9 (parallel [
> > (set (pc)
> > (if_then_else (ne (reg:SI 126)
> > (const_int 1 [0x1]))
> > (label_ref:SI 55)
> > (pc)))
> > (set (reg:SI 126)
> > (plus:SI (reg:SI 126)
> > (const_int -1 [0xffffffff])))
> > (unspec [
> > (const_int 0 [0x0])
> > ] 98)
> > (clobber (reg:BI 70 p6))
> > (clobber (scratch:SI))
> > (clobber (scratch:SI))
> > ]) 1047 {fp_loop_endsi} (expr_list:REG_UNUSED (reg:BI 70 p6)
> > (expr_list:REG_BR_PROB (const_int 9600 [0x2580])
> > (nil))))
> > OUT ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69]
> > IN ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69] [51
> -(O,1,0)-> 69] [47
> -(O,
> > 1,0)-> 69] [43 -(O,1,0)-> 69] [39 -(O,1,0)-> 69]
> > sms-6.c 9 (file, line)
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: Unnecessary regmoves in modulo scheduler?
2009-06-23 13:48 ` Bingfeng Mei
@ 2009-06-23 13:56 ` Revital1 Eres
0 siblings, 0 replies; 10+ messages in thread
From: Revital1 Eres @ 2009-06-23 13:56 UTC (permalink / raw)
To: Bingfeng Mei; +Cc: Ayal Zaks, gcc
Hello,
>
> Thanks. I didn't notice the option. Which approach is generally better
> according to your experience? Producing regmoves or more depedencies?
I think it depends on the target. Having reg-moves could increase
register pressure so using it on targets with small set of registers
could be painful.
Revital
>
> > -----Original Message-----
> > From: Revital1 Eres [mailto:ERES@il.ibm.com]
> > Sent: 23 June 2009 14:40
> > To: Bingfeng Mei
> > Cc: Ayal Zaks; gcc@gcc.gnu.org
> > Subject: Re: Unnecessary regmoves in modulo scheduler?
> >
> > Hello Bingfeng,
> >
> > > I found a true register dependency is always accompanied with a
> > cross-iteration
> > > anti dependency.
> >
> > When -fmodulo-sched-allow-regmoves flag is set some anti-deps
> > edges are not
> > created.
> > Please see add_cross_iteration_register_deps () function in ddg.c.
> >
> > HTH,
> > Revital
> >
> > This should guarantee the true dependence cannot have lifetime
> > > longer than II.
> > >
> > > A --> B true dep (e.g., insn 36 -> insn
> > 38 in the
> > DDG)
> > > B --> A anti dep with distance = 1 (e.g., insn 38 ->
> > insn 36 in the
> > DDG)
> > >
> > > The second dependdency should lead to : Sched_Time(A) + II >(=)
> > Sched_Time(B)
> > > which means Sched_Time(B) - Sched_Time(A) <(=) II and no
> > need for reg
> > move.
> > >
> > > Similarly, an anti register dependency is always accompanied with a
> > cross-iteration
> > > true dependency.
> > >
> > > A --> B anti dep (e.g., insn 36 ->
> > insn 53 in the
> > DDG)
> > > B --> A true dep with distance = 1 (e.g., insn 53 ->
> > insn 36 in the
> > DDG)
> > > We can reach similar conclusion.
> > >
> > > I wonder what other scenario would require to generate reg
> > moves. Am I
> > missing
> > > some obvious points? Thanks in advance.
> > >
> > >
> > > Cheers,
> > > Bingfeng Mei
> > >
> > > Broadcom UK
> > >
> > >
> > > DDG from sms-6.c
> > > SMS loop num: 1, file: sms-6.c, line: 9
> > > Node num: 0
> > > (insn 36 35 37 3 sms-6.c:11 (set (reg:SI 113)
> > > (mem:SI (reg:SI 108 [ ivtmp.44 ]) [4 S4 A32])) 184 {*movwsi}
> > (nil))
> > > OUT ARCS: [36 -(A,0,0)-> 53] [36 -(T,6,0)-> 38]
> > > IN ARCS: [38 -(A,0,1)-> 36] [53 -(T,1,1)-> 36]
> > > Node num: 1
> > > (insn 37 36 38 3 sms-6.c:11 (set (reg:SI 114)
> > > (mem:SI (reg:SI 109 [ ivtmp.42 ]) [5 S4 A32])) 184 {*movwsi}
> > (nil))
> > > OUT ARCS: [37 -(A,0,0)-> 52] [37 -(T,6,0)-> 38]
> > > IN ARCS: [38 -(A,0,1)-> 37] [52 -(T,1,1)-> 37]
> > > Node num: 2
> > > (insn 38 37 39 3 sms-6.c:11 (set (reg:SI 115)
> > > (mult:SI (reg:SI 113)
> > > (reg:SI 114))) 262 {mulsi3} (expr_list:REG_DEAD
> > (reg:SI 114)
> > > (expr_list:REG_DEAD (reg:SI 113)
> > > (nil))))
> > > OUT ARCS: [38 -(A,0,1)-> 37] [38 -(A,0,1)-> 36] [38
> > -(T,8,0)-> 39]
> > > IN ARCS: [39 -(A,0,1)-> 38] [36 -(T,6,0)-> 38] [37 -(T,6,0)-> 38]
> > > Node num: 3
> > > (insn 39 38 40 3 sms-6.c:11 (set (mem:SI (reg:SI 107 [
> > ivtmp.45 ]) [3 S4
> > A32])
> > > (reg:SI 115)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 115)
> > > (nil)))
> > > OUT ARCS: [39 -(A,0,1)-> 38] [39 -(O,1,0)-> 69] [39
> > -(A,0,0)-> 54]
> > > IN ARCS: [54 -(T,1,1)-> 39] [51 -(O,1,1)-> 39] [47
> > -(O,1,1)-> 39] [43
> > -(O,
> > > 1,1)-> 39] [38 -(T,8,0)-> 39]
> > > Node num: 4
> > > (insn 40 39 41 3 sms-6.c:12 (set (reg:SI 116)
> > > (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > > (const_int 4 [0x4])) [4 S4 A32])) 184
> > {*movwsi} (nil))
> > > OUT ARCS: [40 -(A,0,0)-> 53] [40 -(T,6,0)-> 42]
> > > IN ARCS: [42 -(A,0,1)-> 40] [53 -(T,1,1)-> 40]
> > > Node num: 5
> > > (insn 41 40 42 3 sms-6.c:12 (set (reg:SI 117)
> > > (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > > (const_int 4 [0x4])) [5 S4 A32])) 184
> > {*movwsi} (nil))
> > > OUT ARCS: [41 -(A,0,0)-> 52] [41 -(T,6,0)-> 42]
> > > IN ARCS: [42 -(A,0,1)-> 41] [52 -(T,1,1)-> 41]
> > > Node num: 6
> > > (insn 42 41 43 3 sms-6.c:12 (set (reg:SI 118)
> > > (mult:SI (reg:SI 116)
> > > (reg:SI 117))) 262 {mulsi3} (expr_list:REG_DEAD
> > (reg:SI 117)
> > > (expr_list:REG_DEAD (reg:SI 116)
> > > (nil))))
> > > OUT ARCS: [42 -(A,0,1)-> 41] [42 -(A,0,1)-> 40] [42
> > -(T,8,0)-> 43]
> > > IN ARCS: [43 -(A,0,1)-> 42] [40 -(T,6,0)-> 42] [41 -(T,6,0)-> 42]
> > > Node num: 7
> > > (insn 43 42 44 3 sms-6.c:12 (set (mem:SI (plus:SI (reg:SI 107
> > [ ivtmp.45 ])
> > > (const_int 4 [0x4])) [3 S4 A32])
> > > (reg:SI 118)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 118)
> > > (nil)))
> > > OUT ARCS: [43 -(A,0,1)-> 42] [43 -(O,1,0)-> 69] [43
> > -(A,0,0)-> 54]
> > [43 -
> > > (O,1,1)-> 39]
> > > IN ARCS: [54 -(T,1,1)-> 43] [51 -(O,1,1)-> 43] [47
> > -(O,1,1)-> 43] [42
> > -(T,
> > > 8,0)-> 43]
> > > Node num: 8
> > > (insn 44 43 45 3 sms-6.c:13 (set (reg:SI 119)
> > > (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > > (const_int 8 [0x8])) [4 S4 A32])) 184
> > {*movwsi} (nil))
> > > OUT ARCS: [44 -(A,0,0)-> 53] [44 -(T,6,0)-> 46]
> > > IN ARCS: [46 -(A,0,1)-> 44] [53 -(T,1,1)-> 44]
> > > Node num: 9
> > > (insn 45 44 46 3 sms-6.c:13 (set (reg:SI 120)
> > > (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > > (const_int 8 [0x8])) [5 S4 A32])) 184
> > {*movwsi} (nil))
> > > OUT ARCS: [45 -(A,0,0)-> 52] [45 -(T,6,0)-> 46]
> > > IN ARCS: [46 -(A,0,1)-> 45] [52 -(T,1,1)-> 45]
> > > Node num: 10
> > > (insn 46 45 47 3 sms-6.c:13 (set (reg:SI 121)
> > > (mult:SI (reg:SI 119)
> > > (reg:SI 120))) 262 {mulsi3} (expr_list:REG_DEAD
> > (reg:SI 120)
> > > (expr_list:REG_DEAD (reg:SI 119)
> > > (nil))))
> > > OUT ARCS: [46 -(A,0,1)-> 45] [46 -(A,0,1)-> 44] [46
> > -(T,8,0)-> 47]
> > > IN ARCS: [47 -(A,0,1)-> 46] [44 -(T,6,0)-> 46] [45 -(T,6,0)-> 46]
> > > Node num: 11
> > > (insn 47 46 48 3 sms-6.c:13 (set (mem:SI (plus:SI (reg:SI 107
> > [ ivtmp.45 ])
> > > (const_int 8 [0x8])) [3 S4 A32])
> > > (reg:SI 121)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 121)
> > > (nil)))
> > > OUT ARCS: [47 -(A,0,1)-> 46] [47 -(O,1,0)-> 69] [47
> > -(A,0,0)-> 54]
> > [47 -
> > > (O,1,1)-> 43] [47 -(O,1,1)-> 39]
> > > IN ARCS: [54 -(T,1,1)-> 47] [51 -(O,1,1)-> 47] [46 -(T,8,0)-> 47]
> > > Node num: 12
> > > (insn 48 47 49 3 sms-6.c:14 (set (reg:SI 122)
> > > (mem:SI (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > > (const_int 12 [0xc])) [4 S4 A32])) 184
> > {*movwsi} (nil))
> > > OUT ARCS: [48 -(A,0,0)-> 53] [48 -(T,6,0)-> 50]
> > > IN ARCS: [50 -(A,0,1)-> 48] [53 -(T,1,1)-> 48]
> > > Node num: 13
> > > (insn 49 48 50 3 sms-6.c:14 (set (reg:SI 123)
> > > (mem:SI (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > > (const_int 12 [0xc])) [5 S4 A32])) 184
> > {*movwsi} (nil))
> > > OUT ARCS: [49 -(A,0,0)-> 52] [49 -(T,6,0)-> 50]
> > > IN ARCS: [50 -(A,0,1)-> 49] [52 -(T,1,1)-> 49]
> > > Node num: 14
> > > (insn 50 49 51 3 sms-6.c:14 (set (reg:SI 124)
> > > (mult:SI (reg:SI 122)
> > > (reg:SI 123))) 262 {mulsi3} (expr_list:REG_DEAD
> > (reg:SI 123)
> > > (expr_list:REG_DEAD (reg:SI 122)
> > > (nil))))
> > > OUT ARCS: [50 -(A,0,1)-> 49] [50 -(A,0,1)-> 48] [50
> > -(T,8,0)-> 51]
> > > IN ARCS: [51 -(A,0,1)-> 50] [48 -(T,6,0)-> 50] [49 -(T,6,0)-> 50]
> > > Node num: 15
> > > (insn 51 50 52 3 sms-6.c:14 (set (mem:SI (plus:SI (reg:SI 107
> > [ ivtmp.45 ])
> > > (const_int 12 [0xc])) [3 S4 A32])
> > > (reg:SI 124)) 184 {*movwsi} (expr_list:REG_DEAD (reg:SI 124)
> > > (nil)))
> > > OUT ARCS: [51 -(A,0,1)-> 50] [51 -(O,1,0)-> 69] [51
> > -(A,0,0)-> 54]
> > [51 -
> > > (O,1,1)-> 47] [51 -(O,1,1)-> 43] [51 -(O,1,1)-> 39]
> > > IN ARCS: [54 -(T,1,1)-> 51] [50 -(T,8,0)-> 51]
> > > Node num: 16
> > > (insn 52 51 53 3 sms-6.c:14 (set (reg:SI 109 [ ivtmp.42 ])
> > > (plus:SI (reg:SI 109 [ ivtmp.42 ])
> > > (const_int 16 [0x10]))) 220 {addsi3} (nil))
> > > OUT ARCS: [52 -(T,1,1)-> 37] [52 -(T,1,1)-> 41] [52
> > -(T,1,1)-> 45]
> > [52 -
> > > (T,1,1)-> 49] [52 -(T,1,1)-> 52]
> > > IN ARCS: [52 -(T,1,1)-> 52] [49 -(A,0,0)-> 52] [45
> > -(A,0,0)-> 52] [41
> > -(A,
> > > 0,0)-> 52] [37 -(A,0,0)-> 52]
> > > Node num: 17
> > > (insn 53 52 54 3 sms-6.c:14 (set (reg:SI 108 [ ivtmp.44 ])
> > > (plus:SI (reg:SI 108 [ ivtmp.44 ])
> > > (const_int 16 [0x10]))) 220 {addsi3} (nil))
> > > OUT ARCS: [53 -(T,1,1)-> 36] [53 -(T,1,1)-> 40] [53
> > -(T,1,1)-> 44]
> > [53 -
> > > (T,1,1)-> 48] [53 -(T,1,1)-> 53]
> > > IN ARCS: [53 -(T,1,1)-> 53] [48 -(A,0,0)-> 53] [44
> > -(A,0,0)-> 53] [40
> > -(A,
> > > 0,0)-> 53] [36 -(A,0,0)-> 53]
> > > Node num: 18
> > > (insn 54 53 69 3 sms-6.c:14 (set (reg:SI 107 [ ivtmp.45 ])
> > > (plus:SI (reg:SI 107 [ ivtmp.45 ])
> > > (const_int 16 [0x10]))) 220 {addsi3} (nil))
> > > OUT ARCS: [54 -(T,1,1)-> 39] [54 -(T,1,1)-> 43] [54
> > -(T,1,1)-> 47]
> > [54 -
> > > (T,1,1)-> 51] [54 -(T,1,1)-> 54]
> > > IN ARCS: [54 -(T,1,1)-> 54] [51 -(A,0,0)-> 54] [47
> > -(A,0,0)-> 54] [43
> > -(A,
> > > 0,0)-> 54] [39 -(A,0,0)-> 54]
> > > Node num: 19
> > > (jump_insn 69 54 65 3 sms-6.c:9 (parallel [
> > > (set (pc)
> > > (if_then_else (ne (reg:SI 126)
> > > (const_int 1 [0x1]))
> > > (label_ref:SI 55)
> > > (pc)))
> > > (set (reg:SI 126)
> > > (plus:SI (reg:SI 126)
> > > (const_int -1 [0xffffffff])))
> > > (unspec [
> > > (const_int 0 [0x0])
> > > ] 98)
> > > (clobber (reg:BI 70 p6))
> > > (clobber (scratch:SI))
> > > (clobber (scratch:SI))
> > > ]) 1047 {fp_loop_endsi} (expr_list:REG_UNUSED (reg:BI 70 p6)
> > > (expr_list:REG_BR_PROB (const_int 9600 [0x2580])
> > > (nil))))
> > > OUT ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69]
> > > IN ARCS: [69 -(T,1,1)-> 69] [69 -(T,1,1)-> 69] [51
> > -(O,1,0)-> 69] [47
> > -(O,
> > > 1,0)-> 69] [43 -(O,1,0)-> 69] [39 -(O,1,0)-> 69]
> > > sms-6.c 9 (file, line)
> >
> >
> >
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2009-06-23 13:56 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-01-30 16:17 Solve transitive closure issue in modulo scheduling Bingfeng Mei
2009-02-01 23:18 ` Ayal Zaks
2009-02-05 10:45 ` Bingfeng Mei
2009-02-17 12:03 ` Ayal Zaks
2009-03-13 6:43 ` [PATCH] SMS - Pass the actual schedulable rows to compute_split_row Revital1 Eres
2009-06-22 14:10 ` Unnecessary regmoves in modulo scheduler? Bingfeng Mei
2009-06-23 13:41 ` Revital1 Eres
2009-06-23 13:48 ` Bingfeng Mei
2009-06-23 13:56 ` Revital1 Eres
2009-02-07 17:20 ` Solve transitive closure issue in modulo scheduling Daniel Berlin
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