From: <tm_gccmail@mail.kloo.net>
To: Greg McGary <greg@mcgary.org>
Cc: gcc@gcc.gnu.org
Subject: Re: ideas for modeling pipeline with bypass registers?
Date: Tue, 29 Jul 2003 01:29:00 -0000 [thread overview]
Message-ID: <Pine.LNX.4.21.0307281618320.15582-100000@mail.kloo.net> (raw)
In-Reply-To: <ms7k629s3b.fsf@mcgary.org>
On 28 Jul 2003, Greg McGary wrote:
> I'm working on a GCC port to a pipelined machine that has 1 insn
> latency between ALU operation and numbered-register writeback
> (i.e., insn-0: ALU op
> insn-1: ...
> insn-2: ALU op result appears in destination register
>
> In order to make ALU ops available with no latency, there's a special
> "bypass" register that can be used before the register-file writeback.
> This bypass value is available for only one cycle, after which it is
> clobbered by the next ALU op.
I'm assuming this bypass register is an architecturally visible register?
Toshi
next prev parent reply other threads:[~2003-07-28 23:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-28 23:17 Greg McGary
2003-07-29 1:29 ` tm_gccmail [this message]
2003-07-29 6:50 ` Greg McGary
2003-07-29 21:12 ` tm_gccmail
2003-07-29 15:38 Nitin Gupta--SSW, Noida
2003-07-29 17:40 ` Greg McGary
2003-07-29 17:53 Nitin Gupta--SSW, Noida
2003-07-29 18:26 ` Greg McGary
2003-07-30 15:43 Nitin Gupta--SSW, Noida
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