From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22503 invoked by alias); 30 Nov 2001 20:31:54 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 22051 invoked from network); 30 Nov 2001 20:30:28 -0000 Received: from unknown (HELO sensei.ape) (141.108.7.31) by hostedprojects.ges.redhat.com with SMTP; 30 Nov 2001 20:30:28 -0000 Received: from localhost (rossetti@localhost) by sensei.ape (8.9.3/8.9.3) with ESMTP id VAA11492; Fri, 30 Nov 2001 21:30:27 +0100 X-Authentication-Warning: sensei.ape: rossetti owned process doing -bs Date: Fri, 23 Nov 2001 16:20:00 -0000 From: "davide.rossetti" Reply-To: To: Subject: TImode ?inhibited? in main 3.1 branch In-Reply-To: <6F64E8B2-E5BF-11D5-9EC7-003065C86F94@apple.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-SW-Source: 2001-11/txt/msg01143.txt.bz2 hi folks, sure I'm missing something, but I'm wondering why gcc/gcc/c-common.c has this kind of conditionals: #if HOST_BITS_PER_WIDE_INT >= 64 if (mode == TYPE_MODE (intTI_type_node)) return unsignedp ? unsigned_intTI_type_node : intTI_type_node; #endif it ends up being excluded in my build on PIII, so that I can't use typedef int __m128 __attribute__ ((mode (TI))); ... register __v4sf a,b,c; register __v4si d; __m128 e,f,g; ... g = __builtin_ia32_andps((__m128)d,(__m128)a); ... bacause bitwise SSE stuff is marked with TImode args: (define_insn "*sse_andti3_sf_1" [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] "TARGET_SSE" "andps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) so the point is, PIII is somewhat exceptional in having this 128 bit stuff even being 32bit, but ... as it is, SSE support seems (very cautious :) partly unusable.. ciao -- ______/ Rossetti Davide INFN - Roma I - APE group \______________ pho +390649914412 web: http://apegate.roma1.infn.it/~rossetti fax +390649914423 email: davide.rossetti@roma1.infn.it From mboxrd@z Thu Jan 1 00:00:00 1970 From: "davide.rossetti" To: Subject: TImode ?inhibited? in main 3.1 branch Date: Fri, 30 Nov 2001 12:31:00 -0000 Message-ID: References: <6F64E8B2-E5BF-11D5-9EC7-003065C86F94@apple.com> X-SW-Source: 2001-11/msg01644.html Message-ID: <20011130123100.gDeNi40JjNrfGa1mtbZ-KRWtOckJP4GpztuqogBe1Co@z> hi folks, sure I'm missing something, but I'm wondering why gcc/gcc/c-common.c has this kind of conditionals: #if HOST_BITS_PER_WIDE_INT >= 64 if (mode == TYPE_MODE (intTI_type_node)) return unsignedp ? unsigned_intTI_type_node : intTI_type_node; #endif it ends up being excluded in my build on PIII, so that I can't use typedef int __m128 __attribute__ ((mode (TI))); ... register __v4sf a,b,c; register __v4si d; __m128 e,f,g; ... g = __builtin_ia32_andps((__m128)d,(__m128)a); ... bacause bitwise SSE stuff is marked with TImode args: (define_insn "*sse_andti3_sf_1" [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] "TARGET_SSE" "andps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) so the point is, PIII is somewhat exceptional in having this 128 bit stuff even being 32bit, but ... as it is, SSE support seems (very cautious :) partly unusable.. ciao -- ______/ Rossetti Davide INFN - Roma I - APE group \______________ pho +390649914412 web: http://apegate.roma1.infn.it/~rossetti fax +390649914423 email: davide.rossetti@roma1.infn.it