* load multiple
@ 2002-10-14 1:14 N V Krishna
2002-10-14 7:45 ` Andrew Haley
0 siblings, 1 reply; 5+ messages in thread
From: N V Krishna @ 2002-10-14 1:14 UTC (permalink / raw)
To: gcc
Hi,
I am working on a ARM port of gcc. I want to insert 'load
multiple' instructions in the code. If the registers are sequential then I
can see the function arm_gen_load_multiple. But I am unable to insert
instructions , where the destination registers list is not sequential.
ldmea r1,{r2,r5}
Can anyone suggest the debug_rtl output for the above type of instruction?
In the test cases I am testing, the only code where it is using ldm is
when popping registers and that code is directly printed in assembly; no
rtl representation is seen.
Any help would be greatly appreciated.
Warm regards
Krishna
^ permalink raw reply [flat|nested] 5+ messages in thread
* load multiple
2002-10-14 1:14 load multiple N V Krishna
@ 2002-10-14 7:45 ` Andrew Haley
2002-10-14 8:30 ` N V Krishna
0 siblings, 1 reply; 5+ messages in thread
From: Andrew Haley @ 2002-10-14 7:45 UTC (permalink / raw)
To: N V Krishna; +Cc: gcc
N V Krishna writes:
> Hi,
> I am working on a ARM port of gcc. I want to insert 'load
> multiple' instructions in the code. If the registers are sequential then I
> can see the function arm_gen_load_multiple. But I am unable to insert
> instructions , where the destination registers list is not sequential.
>
> ldmea r1,{r2,r5}
>
> Can anyone suggest the debug_rtl output for the above type of instruction?
Can't you use just run ARM gcc and dump the RTL to see what it looks
like?
Andrew.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: load multiple
2002-10-14 7:45 ` Andrew Haley
@ 2002-10-14 8:30 ` N V Krishna
2002-10-15 16:48 ` Richard Henderson
0 siblings, 1 reply; 5+ messages in thread
From: N V Krishna @ 2002-10-14 8:30 UTC (permalink / raw)
To: Andrew Haley; +Cc: gcc
# > Hi,
# > I am working on a ARM port of gcc. I want to insert 'load
# > multiple' instructions in the code. If the registers are sequential then I
# > can see the function arm_gen_load_multiple. But I am unable to insert
# > instructions , where the destination registers list is not sequential.
# >
# > ldmea r1,{r2,r5}
# >
# > Can anyone suggest the debug_rtl output for the above type of instruction?
#
#Can't you use just run ARM gcc and dump the RTL to see what it looks
#like?
No. As I wrote before the only ldm instruction that I am seeing without
consecutive registers is the last load to pop off registers and that
instruction is inserted without using RTL.
Warm regards
Krishna
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: load multiple
2002-10-14 8:30 ` N V Krishna
@ 2002-10-15 16:48 ` Richard Henderson
2002-10-15 19:41 ` N V Krishna
0 siblings, 1 reply; 5+ messages in thread
From: Richard Henderson @ 2002-10-15 16:48 UTC (permalink / raw)
To: N V Krishna; +Cc: Andrew Haley, gcc
On Mon, Oct 14, 2002 at 07:36:24AM -0500, N V Krishna wrote:
> No. As I wrote before the only ldm instruction that I am seeing without
> consecutive registers is the last load to pop off registers and that
> instruction is inserted without using RTL.
You're not looking hard enough then. In particular, try some block moves.
(define_insn "*ldmsi4"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 2 "arm_hard_register_operand" "")
(mem:SI (match_operand:SI 1 "s_register_operand" "r")))
(set (match_operand:SI 3 "arm_hard_register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "arm_hard_register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "arm_hard_register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldm%?ia\\t%1, {%2, %3, %4, %5}"
[(set_attr "type" "load")
(set_attr "predicable" "yes")]
)
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: load multiple
2002-10-15 16:48 ` Richard Henderson
@ 2002-10-15 19:41 ` N V Krishna
0 siblings, 0 replies; 5+ messages in thread
From: N V Krishna @ 2002-10-15 19:41 UTC (permalink / raw)
To: Richard Henderson; +Cc: Andrew Haley, gcc
Hi,
On Tue, 15 Oct 2002, Richard Henderson wrote:
#You're not looking hard enough then. In particular, try some block moves.
Probably you are right.
#(define_insn "*ldmsi4"
# [(match_parallel 0 "load_multiple_operation"
# [(set (match_operand:SI 2 "arm_hard_register_operand" "")
# (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
# (set (match_operand:SI 3 "arm_hard_register_operand" "")
# (mem:SI (plus:SI (match_dup 1) (const_int 4))))
# (set (match_operand:SI 4 "arm_hard_register_operand" "")
# (mem:SI (plus:SI (match_dup 1) (const_int 8))))
# (set (match_operand:SI 5 "arm_hard_register_operand" "")
# (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
# "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
# "ldm%?ia\\t%1, {%2, %3, %4, %5}"
# [(set_attr "type" "load")
# (set_attr "predicable" "yes")]
#)
#
I have seen this somewhere before do not remember the exact
place. I had tried something like the following before posting to the
newsgroup:
----
result = gen_rtx_PARALLEL (VOIDmode,
rtvec_alloc (2));
mem = gen_rtx_MEM (SImode, base_r));
RTX_UNCHANGING_P (mem) = 0;
MEM_IN_STRUCT_P (mem) = 0;
MEM_SCALAR_P (mem) = 1;
XVECEXP (result, 0, 0)
= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, reg1), mem);
mem = gen_rtx_MEM (SImode, plus_constant(base_r,4));
RTX_UNCHANGING_P (mem) = 0;
MEM_IN_STRUCT_P (mem) = 0;
MEM_SCALAR_P (mem) = 1;
XVECEXP (result, 0, 1)
= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, reg2), mem);
return result
---
If the registers reg1 and reg2 are consecutive registers then it works
out, otherwise it fails and the reason is simple : It seems the code above
is for instructions like :
ldmia base_r {reg1-reg2}.
But I want to do
ldmia base_r {reg1,reg2}.
Warm regards
Krishna
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2002-10-16 1:09 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2002-10-14 1:14 load multiple N V Krishna
2002-10-14 7:45 ` Andrew Haley
2002-10-14 8:30 ` N V Krishna
2002-10-15 16:48 ` Richard Henderson
2002-10-15 19:41 ` N V Krishna
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