>>I'm working on a project which involves performing some optimizations
>>and annotating three-address code. We've been looking for some suitable
>>framework which can give us IR (in three-instruction format). We studied
>>many compiler infrastructures like SUIF, trimaran, zephyr and so on.

> I think it would be pretty easy to develop a GCC port to a three
> address architecture(TAA) paper machine.  In fact its probabaly easier
> to do that than any of the *real* chips that GCC has been ported to
> since there are little to *none* of the restrictions that real chips
> have(offset limitations, instruction/register scheduling, addressing
> restrictions, etc).

Here's the machine description file I wrote for the GCC frontend used by
the LLVM compiler infrastructure (http://llvm.cs.uiuc.edu/).  It is a very
abstract description which is used to export an IR from GCC.  It was
derived from the sparc.md file, but stripped down and simplified
drastically...

-Chris

-- 
http://llvm.cs.uiuc.edu/
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