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From: Michael Matz <matz@suse.de>
To: Richard Earnshaw <rearnsha@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>,
		'Mark Mitchell' <mark@codesourcery.com>,
	gcc@gcc.gnu.org
Subject: RE: GCC 4.5.0 Status Report (2009-05-05)
Date: Wed, 06 May 2009 15:56:00 -0000	[thread overview]
Message-ID: <Pine.LNX.4.64.0905061754170.29566@wotan.suse.de> (raw)
In-Reply-To: <1241624792.5723.15.camel@pc960.cambridge.arm.com>

Hi,

On Wed, 6 May 2009, Richard Earnshaw wrote:

> > The easiest solution would be to just make a note that you need the 
> > PIC register and then, when expanding the prologue emit the necessary 
> > instructions.  IMO that makes sense as PIC register setup usually is 
> > something the prologue does, like all the other register setups 
> > necessary.
> 
> That won't work because the PIC register on ARM is a pseudo, so 
> generating it during prologue generation is too late.  It needs to exist 
> before data flow analysis starts on the RTL.

That's fine.  You can generate the pseudo, just not emit the code to load 
it until prologue generation starts.  Dataflow analysis starts only after 
everything is expanded to RTL anyway.  I'll try to cobble up a patch to 
show what I mean, but obviously I'm not very fluent with the ARM backend.


Ciao,
Michael.

  parent reply	other threads:[~2009-05-06 15:56 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-05 16:25 Mark Mitchell
2009-05-06 15:06 ` Richard Earnshaw
2009-05-06 15:10   ` Mark Mitchell
2009-05-06 15:27     ` Ramana Radhakrishnan
2009-05-06 15:45       ` Michael Matz
2009-05-06 15:47         ` Richard Earnshaw
2009-05-06 15:49           ` Richard Guenther
2009-05-06 15:51             ` Richard Earnshaw
2009-05-06 15:56           ` Michael Matz [this message]
2009-05-06 15:58             ` Richard Earnshaw
2009-05-07 14:27 ` cond-optab merge delay? [was Re: GCC 4.5.0 Status Report (2009-05-05)] Paolo Bonzini
2009-05-07 18:06   ` Mark Mitchell
2009-05-08 16:55   ` Ramana Radhakrishnan

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