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Date: Tue, 5 Apr 2022 14:04:45 +0100
From: Mark Rutland <mark.rutland@arm.com>
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Subject: Re: GCC 12 miscompilation of volatile asm (was: Re: [PATCH]
 arm64/io: Remind compiler that there is a memory side effect)
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Sorry, I copied the wrong version of the x86_64 assembly as generated by GCC
11.2.0). Updated below.

On Tue, Apr 05, 2022 at 01:51:30PM +0100, Mark Rutland wrote:
> My x86_64 test case is:
> 
> | unsigned long rdmsr(unsigned long reg)
> | {
> |     unsigned int lo, hi;
> | 
> |     asm volatile(
> |     "rdmsr"
> |     : "=d" (hi), "=a" (lo)
> |     : "c" (reg)
> |     );
> | 
> |     return ((unsigned long)hi << 32) | lo;
> | }
> | 
> | void wrmsr(unsigned long reg, unsigned long val)
> | {
> |     unsigned int lo = val;
> |     unsigned int hi = val >> 32;
> | 
> |     asm volatile(
> |     "wrmsr"
> |     :
> |     : "d" (hi), "a" (lo), "c" (reg)
> |     );
> | }
> | 
> | void msr_rmw_set_bits(unsigned long reg, unsigned long bits)
> | {
> |     unsigned long val;
> | 
> |     val = rdmsr(reg);
> |     val |= bits;
> |     wrmsr(reg, val);
> | }
> | 
> | void func_with_msr_side_effects(unsigned long reg)
> | {
> |     msr_rmw_set_bits(reg, 1UL << 0);
> |     msr_rmw_set_bits(reg, 1UL << 1);
> |     msr_rmw_set_bits(reg, 1UL << 2);
> |     msr_rmw_set_bits(reg, 1UL << 3);
> | }
> 
> Per compiler explorer (https://godbolt.org/z/cveff9hq5) GCC trunk currently
> compiles this as:
> 
> | msr_rmw_set_bits:
> |         mov     rcx, rdi
> |         rdmsr
> |         sal     rdx, 32
> |         mov     eax, eax
> |         or      rax, rsi
> |         or      rax, rdx
> |         mov     rdx, rax
> |         shr     rdx, 32
> |         wrmsr
> |         ret
> | func_with_msr_side_effects:
> |         ret
> 

GCC 11.2 compiles that as:

| rdmsr:
|         mov     rcx, rdi
|         rdmsr
|         sal     rdx, 32
|         mov     eax, eax
|         or      rax, rdx
|         ret
| wrmsr:
|         mov     rax, rsi
|         mov     rdx, rsi
|         shr     rdx, 32
|         mov     rcx, rdi
|         wrmsr
|         ret
| msr_rmw_set_bits:
|         mov     rcx, rdi
|         rdmsr
|         sal     rdx, 32
|         mov     eax, eax
|         or      rax, rsi
|         or      rax, rdx
|         mov     rdx, rax
|         shr     rdx, 32
|         wrmsr
|         ret
| func_with_msr_side_effects:
|         push    rbx
|         mov     rbx, rdi
|         mov     esi, 1
|         call    msr_rmw_set_bits
|         mov     esi, 2
|         mov     rdi, rbx
|         call    msr_rmw_set_bits
|         mov     esi, 4
|         mov     rdi, rbx
|         call    msr_rmw_set_bits
|         mov     esi, 8
|         mov     rdi, rbx
|         call    msr_rmw_set_bits
|         pop     rbx
|         ret

Thanks,
Mark.