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From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Project Revolution <projectrevotpp@hotmail.com>
Cc: Andrew Pinski <pinskia@gmail.com>,
	"gcc@gcc.gnu.org" <gcc@gcc.gnu.org>,
	 "kenixwhisperwind@gmail.com" <kenixwhisperwind@gmail.com>
Subject: Re: GCC generates non-compliant MIPS relocation data? Obscure GNU extension?
Date: Fri, 19 Feb 2021 19:17:08 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.21.2102191835480.2021@angie.orcam.me.uk> (raw)
In-Reply-To: <CWLP265MB31070AD4B869CBC2E2310977C0849@CWLP265MB3107.GBRP265.PROD.OUTLOOK.COM>

On Fri, 19 Feb 2021, Project Revolution via Gcc wrote:

> Gentlemen: this was fixed, although it's a bit of an odd solution. We 
> had to combine both -mno-explicit-relocs and -mno-split-addresses, even 
> though per the MIPS compiler documentation explicit relocs supersedes 
> the split addresses one. Neither of these options on their own work, and 
> it appears as though they're same result individually until you enable 
> both of these. It's really odd, but we're not questioning it since it 
> resolved our issue.

 The GNU extension that permits multiple R_MIPS_HI16 relocations to be 
matched with one R_MIPS_LO16 relocation for the ABIs such as o32 that use 
the REL relocation format lets the compiler make optimisations that would 
otherwise not be possible.  A typical use case is moving a LUI instruction 
targetted by multiple branches into the respective delay slots, resulting 
in overall shrinking of code by one instruction, such as transforming this 
(delay-slot instructions conventionally indented by one space):

	.set	noreorder
# ...
	beq	$2, $3, $L16
	 nop
# ...
$L16:
	lui	$4, %hi(foo)
	lw	$5, %lo(foo)($4)
# ...
	bltz	$4, $L16
	 nop

into this:

	.set	noreorder
# ...
	beq	$2, $3, $L16
	 lui	$4, %hi(foo)
# ...
$L16:
	lw	$5, %lo(foo)($4)
# ...
	bltz	$4, $L16
	 lui	$4, %hi(foo)

(depending on the execution flow, optimisation options and the ISA level 
chosen branch-likely instructions might be used instead).

 I agree the outcome of the years of MIPS psABI development reflected in 
what GCC and GNU binutils produce nowadays hasn't been properly documented 
and sources of information may be scarce.  The original SVR4 MIPS psABI 
document has had its issues and I believe no exact implementation exists, 
including though not limited to SGI IRIX.

 That said attempts were made in the past to document the state of affairs 
and here's one kept by archive.org that actually mentions the feature: 
<https://web.archive.org/web/20140908233719/https://dmz-portal.mips.com/wiki/MIPS_relocation_types#R_MIPS_HI16>.
The original has been lost however in the turbulent history of the various 
MIPS companies.

 I'm glad to hear you have found a usable workaround.  Otherwise I think 
we might consider adding an option to GCC to disable this psABI extension, 
however offhand I am not sure how difficult it would be to implement.

 It looks to me however that you actually have control over the relocation 
processing code you have referred, so how about improving it to handle the 
GNU R_MIPS_HI16 extension as well?

 It should be straightforward as proved by the usual consumers of MIPS 
object code, such as the GNU linker, the Linux kernel module loader, etc.  
It should give you a smaller code footprint too, to say nothing of the 
size regression the use of `-mno-explicit-relocs' usually results in.

 Have you considered it?

  Maciej

  reply	other threads:[~2021-02-19 18:17 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-18 19:57 Project Revolution
2021-02-18 20:28 ` Andrew Pinski
2021-02-18 21:20   ` Project Revolution
2021-02-19  0:54   ` Project Revolution
2021-02-19 18:17     ` Maciej W. Rozycki [this message]
2021-02-28  0:36       ` Maciej W. Rozycki

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