From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 51835 invoked by alias); 16 Mar 2017 08:50:11 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 51726 invoked by uid 89); 16 Mar 2017 08:50:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=BAYES_50,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=wbr, Felix, felix, Jane X-HELO: mx2.suse.de Received: from mx2.suse.de (HELO mx2.suse.de) (195.135.220.15) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 16 Mar 2017 08:50:08 +0000 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 9D4E8AABE; Thu, 16 Mar 2017 08:50:06 +0000 (UTC) Date: Thu, 16 Mar 2017 08:50:00 -0000 From: Richard Biener To: Andrew Senkevich cc: GCC Mailing List , Uros Bizjak , Jeff Law Subject: Re: [RFC] Support register groups in inline asm In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (LSU 67 2015-01-07) MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="-1609908220-443213372-1489654206=:30051" X-SW-Source: 2017-03/txt/msg00094.txt.bz2 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. ---1609908220-443213372-1489654206=:30051 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Content-length: 2832 On Wed, 15 Mar 2017, Andrew Senkevich wrote: > 2016-12-05 16:31 GMT+01:00 Andrew Senkevich : > > 2016-11-16 8:02 GMT+03:00 Andrew Pinski : > >> On Tue, Nov 15, 2016 at 9:36 AM, Andrew Senkevich > >> wrote: > >>> Hi, > >>> > >>> new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use > >>> of register groups. > >>> > >>> To support register groups feature in inline asm needed some extension > >>> with new constraints. > >>> > >>> Current proposal is the following syntax: > >>> > >>> __asm__ (“SMTH %[group], %[single]" : > >>> [single] "+x"(v0) : > >>> [group] > >>> "Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4)); > >>> > >>> where "YgN" constraint specifies group of N consecutive registers > >>> (which is started from register having number as "0 mod > >>> 2^ceil(log2(N))"), > >>> and "1+K" specifies the next registers in the group. > >>> > >>> Is this syntax ok? How to implement it? > >> > >> > >> Have you looked into how AARCH64 back-end handles this via OI, etc. > >> Like: > >> /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */ > >> INT_MODE (OI, 32); > >> > >> /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers > >> (2 d-regs = 1 q-reg = TImode). */ > >> INT_MODE (CI, 48); > >> INT_MODE (XI, 64); > >> > >> > >> And then it implements TARGET_ARRAY_MODE_SUPPORTED_P. target hook? > >> And the x2 types are defined as a struct of an array like: > >> typedef struct int8x8x2_t > >> { > >> int8x8_t val[2]; > >> } int8x8x2_t; > > > > Thanks! > > > > We have to update proposal with changing "+" symbol to "#" specifying > > offset in a group (to avoid overloading the other meaning of “+” > > specifying that operand is both input and output). > > > > So current proposal of syntax is: > > > > __asm__ (“INSTR %[group], %[single]" : > > [single] "+x"(v0) : > > [group] > > "Yg4"(v1), “1#1"(v2), “1#2"(v3), “1#3"(v4)); > > > > where "YgN" constraint specifies group of N consecutive registers > > (which is started from register having number as "0 mod 2^ceil(log2(N))"), > > and "1#K" specifies the next registers in the group. > > > > Some other questions or comments? > > > > What about consensus on this syntax? > > Hi Richard! > > Can we have agreement on this syntax, what do you think? I have no expertise / opinion here. Richard. > > -- > WBR, > Andrew > > -- Richard Biener SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nuernberg) ---1609908220-443213372-1489654206=:30051--