From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9361 invoked by alias); 21 Oct 2009 14:26:07 -0000 Received: (qmail 9210 invoked by uid 22791); 21 Oct 2009 14:26:07 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,SARE_MSGID_LONG40,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mail-pw0-f57.google.com (HELO mail-pw0-f57.google.com) (209.85.160.57) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 21 Oct 2009 14:25:58 +0000 Received: by pwi18 with SMTP id 18so1816794pwi.16 for ; Wed, 21 Oct 2009 07:25:57 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.9.39 with SMTP id 39mr558318wfi.115.1256135157048; Wed, 21 Oct 2009 07:25:57 -0700 (PDT) From: Mohamed Shafi Date: Wed, 21 Oct 2009 15:56:00 -0000 Message-ID: Subject: How to support 40bit GP register To: GCC Content-Type: text/plain; charset=ISO-8859-1 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-10/txt/msg00435.txt.bz2 HI all, I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data registers and 32bit address registers that can be used as general purpose registers. When 40bit registers are used for arithmetic operations or comparison operations GCC generates code assuming that its a 32bit register. Whenever there is a move from address register to data register sign extension is automatically performed by the target. Since the data register is 40bit after some operations sign/zero extension has to be performed for the result to be proper. Take the following test case for example : typedef struct { char b0; char b1; char b2; char b3; char b4; char b5; } __attribute__ ((packed)) b_struct; typedef struct { short a; long b; short c; short d; b_struct e; } __attribute__ ((packed)) a_struct; int main(void) { volatile a_struct *a; volatile a_struct b; a = &b; *a = (a_struct){1,2,3,4}; a->e.b4 = 'c'; if (a->b != 2) abort (); exit (0); } For accessing a->b GCC generates the following code: move.l (sp-16), d3 lsrr.l #<16, d3 move.l (sp-12),d2 asll #<16,d2 or d3,d2 cmpeq.w #<2,d2 jf _L2 Because data registers are 40 bit for 'asll' operation the shift count should be 16+8 or there should be sign extension from 32bit to 40 bits after the 'or' operation. The target has instruction to sign extend from 32bit to 40 bit. Similarly there are other operation that requires sign/zero extension. So is there any way to tell GCC that the data registers are 40bit and there by expect it to generate sign/zero extension accordingly ? Regards, Shafi