From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 38ADF382E2A3 for ; Fri, 20 May 2022 14:21:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 38ADF382E2A3 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24KDhA5o013184; Fri, 20 May 2022 14:21:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g6c4610wf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 May 2022 14:21:46 +0000 Received: from m0098419.ppops.net (m0098419.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 24KEEHI0017508; Fri, 20 May 2022 14:21:46 GMT Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g6c4610w6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 May 2022 14:21:46 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 24KECXMY015836; Fri, 20 May 2022 14:21:45 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma03dal.us.ibm.com with ESMTP id 3g242b5y5c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 May 2022 14:21:45 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 24KELiPN43057546 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 20 May 2022 14:21:44 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6289DBE051; Fri, 20 May 2022 14:21:44 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DC9C0BE054; Fri, 20 May 2022 14:21:43 +0000 (GMT) Received: from [9.160.114.248] (unknown [9.160.114.248]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 20 May 2022 14:21:43 +0000 (GMT) Message-ID: Date: Fri, 20 May 2022 09:21:43 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [RFC Linux patch] powerpc: add documentation for HWCAPs Content-Language: en-US To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org Cc: gcc@gcc.gnu.org, libc-alpha@sourceware.org References: <20220520051528.98097-1-npiggin@gmail.com> From: Paul E Murphy In-Reply-To: <20220520051528.98097-1-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: kOwVJcbc88NNOjcANKrH_TbcwNq-Ao5b X-Proofpoint-ORIG-GUID: 0cgjAOI_ElatKJtsghoIXB0l8tWwyZot X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-20_04,2022-05-20_02,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 bulkscore=0 adultscore=0 phishscore=0 suspectscore=0 impostorscore=0 spamscore=0 mlxscore=0 clxscore=1011 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205200099 X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, NICE_REPLY_A, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 May 2022 14:21:48 -0000 On 5/20/22 12:15 AM, Nicholas Piggin via Gcc wrote: > This takes the arm64 file and adjusts it for powerpc. Feature > descriptions are vaguely handwaved by me. > --- > > Anybody care to expand on or correct the meaning of these entries or > bikeshed the wording of the intro? Many of them are no longer used > anywhere by upstream kernels and even where they are it's not always > quite clear what the exact intent was, a lot of them are old history > and I don't know what or where they are used. > > I may try to get these descriptions pushed into the ABI doc after a > time, but for now they can live in the kernel tree. > > Thanks, > Nick Thanks, this is really helpful. I've been caught off-guard by some of the subtleties in the meanings of these bits at times. I think it would be helpful to share what is implied by the usage of the word "facility" below. It would resolve some of my questions below. > +PPC_FEATURE_HAS_ALTIVEC > + Vector (aka Altivec, VSX) facility is available. I think "(aka Altivec, VSX)" might be more accurately stated as "(aka Altivec)"? > +PPC_FEATURE_HAS_DFP > + DFP facility is available. Maybe something like "Decimal floating point instructions are available to userspace. Individual instruction availability is dependent on the reported architecture version."? > +PPC_FEATURE_HAS_VSX > + VSX facility is available. A small reminder the features are also dependent on architecture version too might be helpful here too. > +PPC_FEATURE2_TAR > + VSX facility is available. Was manipulating the tar spr was once a privileged instruction, is this a hint userspace can use the related instructions? > + > +PPC_FEATURE2_HAS_IEEE128 > + IEEE 128 is available? What instructions/data? Maybe something like "IEEE 128 binary floating point instructions are supported. Individual instruction availability is dependent on the reported architecture version."? > +PPC_FEATURE2_SCV > + scv instruction is available. I think it might be clearer to say "This kernel supports syscalls using the scv instruction". > +PPC_FEATURE2_MMA > + MMA facility is available. Maybe another note that specific instruction availability may depend on the reported architecture version?