From: "Qian, Jianhua" <qianjh@cn.fujitsu.com>
To: "gcc@gcc.gnu.org" <gcc@gcc.gnu.org>
Subject: A problem with one instruction multiple latencies and pipelines
Date: Mon, 7 Sep 2020 06:08:50 +0000 [thread overview]
Message-ID: <d005a34135eb46e185aaaa38cc8d30b7@G08CNEXMBPEKD06.g08.fujitsu.local> (raw)
Hi
I'm adding a new machine model. I have a problem when writing the "define_insn_reservation" for instruction scheduling.
How to write the "define_insn_reservation" for one instruction that there are different latencies and pipelines according to parameter.
For example, the ADD (shifted register) instruction in a64fx
Instruction Option Latency Pipeline
ADD (shifted register) <amount> = 0 1 EX* | EAG*
<amount> = [1-4] && <shift>=LSL 1+1 (EXA + EXA) | (EXB + EXB)
2+1 (EXA + EXA) | (EXB + EXB)
In aarch64.md ADD (shifted register) instruction is defined as following．
(define_insn "*add_<shift>_<mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
(match_operand:GPI 3 "register_operand" "r")))]
""
"add\\t%<w>0, %<w>3, %<w>1, <shift> %2"
[(set_attr "type" "alu_shift_imm")]
)
It could not be distinguished by the type "alu_shift_imm" when writing "define_insn_reservation" for ADD (shifted register).
What should I do?
Regards
Qian
next reply other threads:[~2020-09-07 6:09 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 6:08 Qian, Jianhua [this message]
2020-09-07 7:40 ` Richard Biener
2020-09-07 8:45 ` Qian, Jianhua
2020-09-07 11:58 ` Richard Biener
2020-09-07 20:20 ` Richard Sandiford
2020-09-08 5:34 ` Qian, Jianhua
2020-09-09 21:22 ` Segher Boessenkool
2020-09-10 5:01 ` Qian, Jianhua
2020-09-10 10:04 ` Richard Sandiford
2020-09-10 23:00 ` Segher Boessenkool
2020-09-11 7:44 ` Richard Sandiford
2020-09-11 13:58 ` Segher Boessenkool
2020-09-14 5:41 ` Qian, Jianhua
2020-09-14 9:55 ` Richard Sandiford
2020-09-14 18:41 ` Segher Boessenkool
2020-09-14 19:35 ` Richard Sandiford
2020-09-14 22:14 ` Segher Boessenkool
2020-09-11 13:30 ` Richard Earnshaw
2020-09-14 2:53 ` Qian, Jianhua
2020-09-14 9:08 ` Richard Earnshaw
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