PowerPC lwsync Instruction

PowerPC lwsync Instruction

[Joel Sherrill]

Hi,

I ran into something tracking down a test
failure on psim and now thing there is a
target specific issue that needs addressing.

libstdc++-v3/config/cpu/powerpc/atomic_word.h
uses the lwsync instruction if __NO_LWSYNC__
is not defined. 

psim does not implement the lwsync instruction.
I checked my 601, 603, and 403 manuals and did
not find this instruction in any of them.

I think the powerpc port is enabling this instruction
on variants that don't have it.  Which PowerPC
cores have this instruction?

It should be fairly straightforward to address since
it is just a matter of setting the __NO_LWSYNC__
macro correctly for each CPU variant.

Thanks.

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill@OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
   Support Available             (256) 722-9985

Re: PowerPC lwsync Instruction

[Andrew Pinski]

On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
<joel.sherrill@oarcorp.com> wrote:
> Hi,
>
> I ran into something tracking down a test
> failure on psim and now thing there is a
> target specific issue that needs addressing.

lwsync is sync with the bit 9 set.  So it should be ok as it was a
reserved field and was supposed to be ignored on the hardware which
did not implement those bits and have it as a sync (but I could be
wrong).

The Power ISA 2.05 describes the sync/lwsync behavior but I can't find
where it says it is ignored if not implemented.  I bet you have to
goto the ISA for those processors to find what is the current behavior
for sure.

Thanks,
Andrew Pinski

Re: PowerPC lwsync Instruction

[Joel Sherrill]

Andrew Pinski wrote:
> On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
> <joel.sherrill@oarcorp.com> wrote:
>   
>> Hi,
>>
>> I ran into something tracking down a test
>> failure on psim and now thing there is a
>> target specific issue that needs addressing.
>>     
>
> lwsync is sync with the bit 9 set.  So it should be ok as it was a
> reserved field and was supposed to be ignored on the hardware which
> did not implement those bits and have it as a sync (but I could be
> wrong).
>   
I don't have access to a real 603e of this vintage but
my Sept 1995 603e User's Manual shows the sync
instruction has having:

0-5      - all 1's (value in table is 31)
6-20   - all 0's (dark grey indicating not implemented)
21-30 - 598
31       - 0

So bit 9 being 1 could be ignored or it could cause
a bad instruction fault.  psim makes it a fault.
> The Power ISA 2.05 describes the sync/lwsync behavior but I can't find
> where it says it is ignored if not implemented.  I bet you have to
> goto the ISA for those processors to find what is the current behavior
> for sure.
>
>   
My 1994 copy of "PowerPC Microprocessor Architecture:
The Programming Environment" shows the bits that are
0 in the 603e manual as reserved.

I really don't know what to make of this now.  Should
gcc not generate lwsync for a 603e and psim is right
Or should psim be fixed to allow bit 9 to be set?

And if psim should be fixed, can you explain how to change
this?  I have never been able to grok this format and this
seems like the simplest possible change. :D


0.31,6./,11./,16./,21.598,31./:X::sync:Synchronize
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  1,  0
    /* do nothing */

What do you have to do to that first line to say the value
of bit 9 doesn't matter?  And where is this explained
in the code? :-D

I can scan the pages and email them to you if you like.

> Thanks,
> Andrew Pinski
>   


-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill@OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
   Support Available             (256) 722-9985

Re: PowerPC lwsync Instruction

[Joe Buck]

On Thu, Jun 19, 2008 at 03:50:34PM -0500, Joel Sherrill wrote:

> >On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
> ><joel.sherrill@oarcorp.com> wrote:
> >  
> >>Hi,
> >>
> >>I ran into something tracking down a test
> >>failure on psim and now thing there is a
> >>target specific issue that needs addressing.
> >>    
> >
Andrew Pinski wrote:
> >lwsync is sync with the bit 9 set.  So it should be ok as it was a
> >reserved field and was supposed to be ignored on the hardware which
> >did not implement those bits and have it as a sync (but I could be
> >wrong).

Based on

http://gcc.gnu.org/ml/gcc-patches/2006-11/msg01238.html

it appears that it is not ignored, but rather traps, on at least some
hardware.  As a rule (thanks to some bad experiences with the Motorola
68000) processor architects tend to make sure that reserved bits and
unused bits generate a trap, otherwise the software developers start using
those bits for some other purpose and constrain future processor
development.

> I really don't know what to make of this now.  Should
> gcc not generate lwsync for a 603e and psim is right
> Or should psim be fixed to allow bit 9 to be set?

If psim's going to support both older and newer processors,
simulated, it appears it has to depend on the specific processor
being simulated (so psim should make both behaviors possible).

Re: PowerPC lwsync Instruction

[Joel Sherrill]

Joe Buck wrote:
> On Thu, Jun 19, 2008 at 03:50:34PM -0500, Joel Sherrill wrote:
>
>   
>>> On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
>>> <joel.sherrill@oarcorp.com> wrote:
>>>
>>>       
>>>> Hi,
>>>>
>>>> I ran into something tracking down a test
>>>> failure on psim and now thing there is a
>>>> target specific issue that needs addressing.
>>>>
>>>>         
> Andrew Pinski wrote:
>   
>>> lwsync is sync with the bit 9 set.  So it should be ok as it was a
>>> reserved field and was supposed to be ignored on the hardware which
>>> did not implement those bits and have it as a sync (but I could be
>>> wrong).
>>>       
>
> Based on
>
> http://gcc.gnu.org/ml/gcc-patches/2006-11/msg01238.html
>
> it appears that it is not ignored, but rather traps, on at least some
> hardware.  As a rule (thanks to some bad experiences with the Motorola
> 68000) processor architects tend to make sure that reserved bits and
> unused bits generate a trap, otherwise the software developers start using
> those bits for some other purpose and constrain future processor
> development.
>   
I agree completely and my 13 year old 603e manual shows
bit 9 as reserved and 0.  So using your argument,
gcc should not generate an lwsync for 603e.

Is the set of CPU models gcc can generate an lwsync for
to generous?

>> I really don't know what to make of this now.  Should
>> gcc not generate lwsync for a 603e and psim is right
>> Or should psim be fixed to allow bit 9 to be set?
>>     
>
> If psim's going to support both older and newer processors,
> simulated, it appears it has to depend on the specific processor
> being simulated (so psim should make both behaviors possible).
>   
Yep.  But I don't see anything too new in the
set of 601, 603, 603e and 604. :-D

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill@OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
   Support Available             (256) 722-9985

Re: PowerPC lwsync Instruction

[Gabriel Paubert]

On Thu, Jun 19, 2008 at 03:50:34PM -0500, Joel Sherrill wrote:
> Andrew Pinski wrote:
> >On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
> ><joel.sherrill@oarcorp.com> wrote:
> >  
> >>Hi,
> >>
> >>I ran into something tracking down a test
> >>failure on psim and now thing there is a
> >>target specific issue that needs addressing.
> >>    
> >
> >lwsync is sync with the bit 9 set.  So it should be ok as it was a
> >reserved field and was supposed to be ignored on the hardware which
> >did not implement those bits and have it as a sync (but I could be
> >wrong).
> >  
> I don't have access to a real 603e of this vintage but
> my Sept 1995 603e User's Manual shows the sync
> instruction has having:
> 
> 0-5      - all 1's (value in table is 31)
> 6-20   - all 0's (dark grey indicating not implemented)
> 21-30 - 598
> 31       - 0
> 

I have 6 PPC603ev (5 at revision 2.1 and one at 18.1
according to /proc/cpuinfo, some of them running almost 
nonstop for 11 years, all of them for 7 years at least) 
and they all accept an: 

asm volatile("lwsync" : : : "memory");

between two printf() without trapping  (I see the output of
the second printf).

I also tried with ptesync, which is also accepted.

	Regards,
	Gabriel