From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B23503858D37 for ; Wed, 2 Mar 2022 11:49:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B23503858D37 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 18D5313D5; Wed, 2 Mar 2022 03:49:44 -0800 (PST) Received: from [10.57.20.251] (unknown [10.57.20.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 65E0C3F70D; Wed, 2 Mar 2022 03:49:43 -0800 (PST) Message-ID: Date: Wed, 2 Mar 2022 11:49:41 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: ARM Cortex-R5F Support Content-Language: en-GB To: Kinsey Moore , gcc@gcc.gnu.org Cc: Joel Sherrill References: From: Richard Earnshaw In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3491.0 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, NICE_REPLY_A, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Mar 2022 11:49:46 -0000 On 01/03/2022 16:23, Kinsey Moore wrote: > Hi, > > I'm looking at working on Cortex-R5F support for RTEMS, but it seems as > if latest GCC supports the Cortex-R5. This R5 has implicit FPU support > which would make it really R5F. The ARM reference page on this core > (https://developer.arm.com/Processors/Cortex-R5) specifies that the FPU > is optional. I see that the FPU support can probably be disabled using > the nofp option to achieve Cortex-R5 support, but I was wondering why > this is handled differently from the Cortex-R4[F] support since that is > broken out into two different CPU entries in gcc/config/arm/arm-cpus.in. > It appears that R7 and R8 are handled the same way as R5. > > Is the R4/R4F just the legacy way of handling this and R5/7/8 are the > new way? > Arm no-longer gives distinct product names for products that come in multiple guises. Another example of this is that many armv8-a products have an optional crypto unit but have the same product name. So to answer your question more directly, the -mcpu=cortex-r5 will by default be considered to have an FPU, provided that the compiler was built with --with-fpu=auto (the default). If you specify --with-float-abi=soft, then even if the product has an FPU, or for some cases a SIMD unit, then these will never be used. So I'd recommend: For FP support: -mcpu=cortex-r5 -mfloat-abi=hard For no FP support: -mcpu=cortex-r5 -mfloat-abi=soft There's also a mid-way variant of -mcpu=cortex-r5 -mfloat-abi=softfp, which would use the FP hardware but use the soft-float calling conventions; this code is abi-compatible with the no-fp variant above. HTH, R. > > Thanks, > > Kinsey >