Re: avr compilation

["Paulo J. Matos" <pocmatos@gmail.com>]

On 18/03/11 10:08, WANG.Jiong wrote:
> This may related with subreg regmove finding
> Suggest specifiy -fdump-rtl-regmove to see what happen after this pass
> Maybe avr need a target dependent regmove pass to handle this
>

It doesn't look like it's regmove, whose result looks pretty sane:
;; Pred edge  ENTRY [100.0%]  (fallthru)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)

(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)

(insn 5 2 6 2 add.c:5 (set (reg:HI 42)
         (mem/c/i:HI (symbol_ref:HI ("y") [flags 0x2] <var_decl 
0x7f40954201e0 y>) [2 y+0 S2 A8])) 8 {*movhi} (nil))

(insn 6 5 7 2 add.c:5 (set (reg:HI 44 [ x ])
         (mem/c/i:HI (symbol_ref:HI ("x") [flags 0x2] <var_decl 
0x7f4095420140 x>) [2 x+0 S2 A8])) 8 {*movhi} (nil))

(insn 7 6 25 2 add.c:5 (set (reg:HI 42)
         (plus:HI (reg:HI 42)
             (reg:HI 44 [ x ]))) 20 {*addhi3} (expr_list:REG_DEAD 
(reg:HI 44 [ x ])
         (nil)))

(insn 25 7 26 2 add.c:7 (set (reg:QI 24 r24)
         (subreg:QI (reg:HI 42) 0)) 4 {*movqi} (nil))

(insn 26 25 18 2 add.c:7 (set (reg:QI 25 r25 [+1 ])
         (subreg:QI (reg:HI 42) 1)) 4 {*movqi} (expr_list:REG_DEAD 
(reg:HI 42)
         (nil)))

(insn 18 26 0 2 add.c:7 (use (reg/i:HI 24 r24)) -1 (nil))
;; End of basic block 2 -> ( 1)


If psr 42 and 44 are allocated to the proper registers, i.e. 42 is 
allocated to the return registers insn 25/26 could be deleted, however, 
that's not what happens after register allocation:

;; Pred edge  ENTRY [100.0%]  (fallthru)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)

(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)

(insn 5 2 6 2 add.c:5 (set (reg:HI 18 r18 [42])
         (mem/c/i:HI (symbol_ref:HI ("y") [flags 0x2] <var_decl 
0x7f40954201e0 y>) [2 y+0 S2 A8])) 8 {*movhi} (nil))

(insn 6 5 7 2 add.c:5 (set (reg:HI 24 r24 [orig:44 x ] [44])
         (mem/c/i:HI (symbol_ref:HI ("x") [flags 0x2] <var_decl 
0x7f4095420140 x>) [2 x+0 S2 A8])) 8 {*movhi} (nil))

(insn 7 6 25 2 add.c:5 (set (reg:HI 18 r18 [42])
         (plus:HI (reg:HI 18 r18 [42])
             (reg:HI 24 r24 [orig:44 x ] [44]))) 20 {*addhi3} (nil))

(insn 25 7 26 2 add.c:7 (set (reg:QI 24 r24)
         (reg:QI 18 r18 [42])) 4 {*movqi} (nil))

(insn 26 25 18 2 add.c:7 (set (reg:QI 25 r25 [+1 ])
         (reg:QI 19 r19 [+1 ])) 4 {*movqi} (nil))

(insn 18 26 27 2 add.c:7 (use (reg/i:HI 24 r24)) -1 (nil))
;; End of basic block 2 -> ( 1)

So, I guess it's probably something else...

>
> Best,
> Jiong
>
> On 03/18/2011 04:47 PM, Paulo J. Matos wrote:
>> Hi all,
>>
>> I am looking at the avr backend in order to try to sort some things
>> out on my own backend.
>>
>> One of the tests I am doing is by compiling the following:
>> int x = 0x1010;
>> int y = 0x0101;
>>
>> int add(void)
>> {
>> return x+y;
>> }
>>
>> It compiles to (in gcc-4.3.5_avr with -Os)
>> add:
>> /* prologue: function */
>> /* frame size = 0 */
>> lds r18,y
>> lds r19,(y)+1
>> lds r24,x
>> lds r25,(x)+1
>> add r18,r24
>> adc r19,r25
>> mov r24,r18
>> mov r25,r19
>> /* epilogue start */
>> ret
>>
>> I don't know much avr assembler so bear with me but I would expect
>> this to be written:
>> add:
>> /* prologue: function */
>> /* frame size = 0 */
>> lds r18,y
>> lds r19,(y)+1
>> lds r24,x
>> lds r25,(x)+1
>> add r24,r18
>> adc r25,r19
>> /* epilogue start */
>> ret
>>
>> By inverting the add arguments we save two mov instructions.
>>
>> If it can be written like this any ideas on why GCC is avoiding it?
>>
>> Cheers,
>>
>> --
>> PMatos
>>
>
>