From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17847 invoked by alias); 20 Oct 2011 12:05:24 -0000 Received: (qmail 17829 invoked by uid 22791); 20 Oct 2011 12:05:23 -0000 X-SWARE-Spam-Status: No, hits=-1.2 required=5.0 tests=AWL,BAYES_00,RCVD_NUMERIC_HELO,RP_MATCHES_RCVD,SPF_HELO_PASS,TW_RQ X-Spam-Check-By: sourceware.org Received: from lo.gmane.org (HELO lo.gmane.org) (80.91.229.12) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 20 Oct 2011 12:05:03 +0000 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1RGrMq-0003gl-TF for gcc@gcc.gnu.org; Thu, 20 Oct 2011 14:05:00 +0200 Received: from 193.128.72.68 ([193.128.72.68]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Thu, 20 Oct 2011 14:05:00 +0200 Received: from paulo by 193.128.72.68 with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Thu, 20 Oct 2011 14:05:00 +0200 To: gcc@gcc.gnu.org From: "Paulo J. Matos" Subject: Re: Expanding instructions with condition codes inter-deps Date: Thu, 20 Oct 2011 12:46:00 -0000 Message-ID: References: <4E9E0775.3020303@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 In-Reply-To: <4E9E0775.3020303@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2011-10/txt/msg00344.txt.bz2 On 19/10/11 00:10, Richard Henderson wrote: > > The thing that's almost certainly missing is that the NAND pattern > must SET your flags register, not simply clobber it. Otherwise the > dependency between the ADDC and the NAND will never be created properly. > I understand that there's a missing SET of RCC in the NAND. However, what's the set source, we are really not sure what we are setting RCC to. Also, I am following the pattern set by rx and mn10300 of using a pseudo register for the flags. So my nadd pattern is: (define_insn "negqi2" [(set (match_operand:QI 0 "register_operand" "=c") (neg:QI (match_operand:QI 1 "register_operand" "0"))) (clobber (reg:CC RCC))] "" { operands[2] = const0_rtx; return "nadd\\t%0,%2"; }) (define_insn "*negqi2_flags" [(set (match_operand:QI 0 "register_operand" "=c") (neg:QI (match_operand:QI 1 "register_operand" "0"))) (set (reg RCC) (compare (neg:QI (match_dup 1)) (const_int 0)))] "reload_completed && xap_match_ccmode(insn, CCmode)" { operands[2] = const0_rtx; return "nadd\\t%0,%2"; }) It doesn't make sense to me, to add a (set (reg:C RCC) (neg:QI (match_dup 1))) into the parallel since this is going to class with the already existing _flags version of negqi which sets RCC. >> (for example, it would be ok to output negqi2, xorqi3 and >> addc_internal since xorqi3 only sets N and Z, not the Carry bit) > > For that you'd have to model all of the flags bits independently. > I don't believe any target has found that level of complexity to > be worth the trouble. > > So, almost certainly, you don't. > Well, if I am only interested in th Carry flag, I can as well just bother about that. It wouldn't be much of a trouble since I already have the mode CC_Cmode to model instruction which only set this flag. -- PMatos