From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10607 invoked by alias); 6 Dec 2001 23:01:29 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 10269 invoked from network); 6 Dec 2001 23:01:19 -0000 Received: from unknown (HELO geoffk.org) (205.180.231.50) by sources.redhat.com with SMTP; 6 Dec 2001 23:01:19 -0000 Received: (from geoffk@localhost) by geoffk.org (8.9.3/8.9.3) id PAA04379; Thu, 6 Dec 2001 15:00:29 -0800 To: Rayson Ho CC: gcc@gcc.gnu.org Subject: Re: instruction sync -- need to preserve order References: <20011206212947.86162.qmail@web11401.mail.yahoo.com> Reply-to: Geoff Keating From: Geoff Keating Date: Thu, 06 Dec 2001 15:04:00 -0000 In-Reply-To: Rayson Ho's message of "Thu, 6 Dec 2001 13:29:47 -0800 (PST)" Message-ID: X-Mailer: Gnus v5.5/Emacs 20.3 X-SW-Source: 2001-12/txt/msg00320.txt.bz2 Rayson Ho writes: > Hi, > > How can I make sure that gcc does not schedule instructions across a > memory barrier?? I am porting a threads library from AIX to PPC Linux, > and on AIX, the compiler has a build-in instruction that allows me to > do that. What you really want to do is specify to GCC that the memory barrier affects memory, like this (assuming the barrier you're using is the "sync" instruction): asm ("sync" : : : "memory"); Instructions that don't affect memory will still be scheduled across it, but memory will be consistent. -- - Geoffrey Keating