From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6175 invoked by alias); 2 Jul 2009 19:46:08 -0000 Received: (qmail 6156 invoked by uid 22791); 2 Jul 2009 19:46:06 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=AWL,BAYES_00,SPF_PASS X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (216.239.45.13) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 02 Jul 2009 19:45:58 +0000 Received: from wpaz17.hot.corp.google.com (wpaz17.hot.corp.google.com [172.24.198.81]) by smtp-out.google.com with ESMTP id n62JjuXn013264 for ; Thu, 2 Jul 2009 12:45:56 -0700 Received: from pxi38 (pxi38.prod.google.com [10.243.27.38]) by wpaz17.hot.corp.google.com with ESMTP id n62Jjrxl010088 for ; Thu, 2 Jul 2009 12:45:53 -0700 Received: by pxi38 with SMTP id 38so883162pxi.14 for ; Thu, 02 Jul 2009 12:45:53 -0700 (PDT) Received: by 10.114.208.12 with SMTP id f12mr599445wag.48.1246563953004; Thu, 02 Jul 2009 12:45:53 -0700 (PDT) Received: from localhost.localdomain.google.com (adsl-71-133-8-30.dsl.pltn13.pacbell.net [71.133.8.30]) by mx.google.com with ESMTPS id m25sm4841634waf.9.2009.07.02.12.45.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 12:45:51 -0700 (PDT) To: Mohamed Shafi Cc: GCC Subject: Re: About feasibility of implementing an instruction References: From: Ian Lance Taylor Date: Thu, 02 Jul 2009 19:46:00 -0000 In-Reply-To: (Mohamed Shafi's message of "Thu\, 2 Jul 2009 10\:29\:15 +0530") Message-ID: User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-System-Of-Record: true X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-07/txt/msg00062.txt.bz2 Mohamed Shafi writes: > I just want to know about the feasibility of implementing an > instruction for a port in gcc 4.4 > The target has 40 bit register where the normal load/store/move > instructions will be able to access the 32 bits of the register. In > order to move data into the rest of the register [b32 to b39] the data > has to be stored into a 32bit memory location. The data should be > stored in such a way that if it is stored for 0-7 in memory the data > can be moved to b32-b39 of a even register and if the data in the > memory is stored in 16-23 of the memory word then it can be moved to > b32-b39 of a odd register. Hope i make myself clear. > > Will it be possible to implement this in the gcc back-end so that the > particular instruction is supported? In general, the gcc backend can do anything, so, yes, this can be supported. It sounds like this is not a general purpose register, so I would probably do it using a builtin function. If you need to treat it as a general purpose register (i.e., the register is managed by the register allocator) then you will need a secondary reload to handle this. Ian