From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8942 invoked by alias); 18 Sep 2009 04:49:10 -0000 Received: (qmail 8934 invoked by uid 22791); 18 Sep 2009 04:49:08 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_32,J_CHICKENPOX_74,SPF_PASS X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (216.239.33.17) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 18 Sep 2009 04:49:04 +0000 Received: from zps18.corp.google.com (zps18.corp.google.com [172.25.146.18]) by smtp-out.google.com with ESMTP id n8I4n0Io025406 for ; Fri, 18 Sep 2009 05:49:01 +0100 Received: from an-out-0708.google.com (anab38.prod.google.com [10.100.53.38]) by zps18.corp.google.com with ESMTP id n8I4mvYj022205 for ; Thu, 17 Sep 2009 21:48:58 -0700 Received: by an-out-0708.google.com with SMTP id b38so388058ana.23 for ; Thu, 17 Sep 2009 21:48:57 -0700 (PDT) Received: by 10.101.102.16 with SMTP id e16mr1010939anm.84.1253249337610; Thu, 17 Sep 2009 21:48:57 -0700 (PDT) Received: from localhost.localdomain.google.com (adsl-71-133-8-30.dsl.pltn13.pacbell.net [71.133.8.30]) by mx.google.com with ESMTPS id c14sm84357ana.0.2009.09.17.21.48.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 17 Sep 2009 21:48:56 -0700 (PDT) To: "Amker.Cheng" Cc: gcc@gcc.gnu.org Subject: Re: Is Non-Blocking cache supported in GCC? References: From: Ian Lance Taylor Date: Fri, 18 Sep 2009 04:49:00 -0000 In-Reply-To: (Amker Cheng's message of "Fri\, 18 Sep 2009 10\:05\:43 +0800") Message-ID: User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-System-Of-Record: true X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-09/txt/msg00313.txt.bz2 "Amker.Cheng" writes: > Recently I found two relative old papers about non-blocking cache, > etc. which are : > > 1) Reducing memory latency via non-blocking and prefetching > caches. BY Tien-Fu Chen and Jean-Loup Baer. > 2) Data Prefetching:A Cost/Performance Analysis BY Chris Metcalf > > It seems the hardware facility does have the potential to improve the > performance with > compiler's assistance(especially instruction scheduling). while on the > other hand, lifting ahead > load instructions may resulting in increasing register pressure. > > So I'm thinking : > 1, Has anyone from gcc folks done any investigation on this topic yet, > or any statistic data based on gcc available? > 2, Does GCC(in any release version) supports it in any targets(such as > mips 24ke) with this hardware feature? > If not currently, does it possible to support it by using target > definition macros and functions? gcc is able to generate prefetches in loops, via the -fprefetch-loop-arrays option. There are various related parameters, prefetch-latency, l1-cache-line-size, etc. I don't know how well this works. To the extent that it does work, it is supported in the MIPS backend, and should work on the MIPS 24ke. Ian