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From: Ian Lance Taylor <iant@google.com>
To: Revital Eres <revital.eres@linaro.org>
Cc: gcc@gcc.gnu.org
Subject: Re: A question about sched_analyze_insn in sched-deps.c
References: <CAHz1=dUzgAzbpxGSw1W_Yc1km6YCxj0dahOwOp5VYu3RJ7kNsA@mail.gmail.com>
Date: Wed, 10 Aug 2011 15:57:00 -0000
In-Reply-To: <CAHz1=dUzgAzbpxGSw1W_Yc1km6YCxj0dahOwOp5VYu3RJ7kNsA@mail.gmail.com>	(Revital Eres's message of "Wed, 10 Aug 2011 17:24:57 +0300")
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Revital Eres <revital.eres@linaro.org> writes:

> I appriciate explanation regarding the following piece of code in
> sched_analyze_insn function (sched-deps.c): When handling jump instruction
> dependence edges are created between the jump instruction and memory
> writes and volatile reads and I'm not quite sure the reason why.

Jump instructions can be conditional.  Note the check for whether the
next instruction is a barrier.

Ian