Re: A problem with one instruction multiple latencies and pipelines

[Richard Sandiford <richard.sandiford@arm.com>]

Segher Boessenkool <segher@kernel.crashing.org> writes:
>> Although this looks/sounds complicated, the advantage is that everything
>> remains up-to-date.  If we instead added a second attribute and only
>> defined it for instructions like *add_<shift>_<mode>, other instructions
>> (including config/arm instructions) would still have type alu_shift_imm
>> but would have a shift_imm_value of "none".
>
> I would make an attribute for the mode (or data size really), and one
> that says the insn uses shifted data (since many arm insns have that,
> just like record form on PowerPC is everywhere).  And you can have that
> one filled "by magic" usually!

I don't think this is really answering my point above though.
What I meant is: we currently have several instructions in config/arm
and config/aarch64 that have type alu_shift_imm.  If we add some new
on-the-side attributes A, but only update *some* of the alu_shift_imm
instructions to define A (either directly or indirectly), then the other
alu_shift_imm instructions will have the default values for A.
This probably isn't the intended effect.  Ideally, every alu_shift_imm
instruction would specify correct attribute values for A (specifically,
to indicate whether the shift value is in [1, 4] or not).

In contrast, one advantage of replacing the existing alu_shift_imm type
with two new types is that any existing reference to the old type will
cause a build failure.  So keeping everything in a single type
attributes gives us static type checking that the information for each
(former) alu_shift_imm instruction is complete.  Similarly for any other
type that needs to be split in the same way.

I realise this won't convince you, and I'm not trying to. :-)

Thanks,
Richard