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From: Andreas Schwab <schwab@suse.de>
To: Peng Fan <peng.fan@nxp.com>
Cc: "gcc\@gcc.gnu.org" <gcc@gcc.gnu.org>,  "james.greenhalgh\@arm.com" <james.greenhalgh@arm.com>,  "nd\@arm.com" <nd@arm.com>,  "jailhouse-dev\@googlegroups.com" <jailhouse-dev@googlegroups.com>,  "will.deacon\@arm.com" <will.deacon@arm.com>,  Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
References: <DB7PR04MB4490342F0A0FE96668B25F3188660@DB7PR04MB4490.eurprd04.prod.outlook.com>
X-Yow: I always liked FLAG DAY!!
Date: Wed, 13 Feb 2019 13:59:00 -0000
In-Reply-To: <DB7PR04MB4490342F0A0FE96668B25F3188660@DB7PR04MB4490.eurprd04.prod.outlook.com>	(Peng Fan's message of "Wed, 13 Feb 2019 07:13:21 +0000")
Message-ID: <mvmk1i3rdqa.fsf@suse.de>
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On Feb 13 2019, Peng Fan <peng.fan@nxp.com> wrote:

> static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
> {
>         u32 ret;
>         u64 test, tmp;
>
>         BITOPT_ALIGN(nr, addr);
>
>         /* AARCH64_TODO: using Inner Shareable DMB at the moment,
>          * revisit when we will deal with shareability domains */
>
>         do {
>                 asm volatile (
>                         "ldxr   %3, %2\n\t"
>                         "ands   %1, %3, %4\n\t"
>                         "b.ne   1f\n\t"
>                         "orr    %3, %3, %4\n\t"
>                         "1:\n\t"
>                         "stxr   %w0, %3, %2\n\t"
>                         "dmb    ish\n\t"
>                         : "=r" (ret), "=&r" (test),
>                           "+Q" (*(volatile unsigned long *)addr),
>                           "=r" (tmp)
>                         : "r" (1ul << nr));

%3 is modified early, but not marked earlyclobber.

Andreas.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
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