* sse? sse2? mmx?
@ 2002-05-16 12:36 Neal D. Becker
2002-05-17 6:07 ` Jan Hubicka
0 siblings, 1 reply; 2+ messages in thread
From: Neal D. Becker @ 2002-05-16 12:36 UTC (permalink / raw)
To: gcc
What are suggested settings to optimize double float performance on
athlon-xp?
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: sse? sse2? mmx?
2002-05-16 12:36 sse? sse2? mmx? Neal D. Becker
@ 2002-05-17 6:07 ` Jan Hubicka
0 siblings, 0 replies; 2+ messages in thread
From: Jan Hubicka @ 2002-05-17 6:07 UTC (permalink / raw)
To: Neal D. Becker; +Cc: gcc
> What are suggested settings to optimize double float performance on
> athlon-xp?
Athlon-xp support SSE1 instruction set only and it has no support for doubles,
only for floats, so there is no way to use the extensions.
Next generation of AMD chips will, as you can see in the description of x86-64
architecture adn AMD's pages.
For Pentium4 it is -march=pentium4 -mfpmath=see
For Athlon-xp/floats it is -march=athlon-xp -mfpmath=sse
Honza
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2002-05-17 12:38 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-05-16 12:36 sse? sse2? mmx? Neal D. Becker
2002-05-17 6:07 ` Jan Hubicka
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).