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* [binutils-gdb] sim: ppc: migrate to standard uintXX_t types
@ 2022-01-06 6:22 Michael Frysinger
0 siblings, 0 replies; only message in thread
From: Michael Frysinger @ 2022-01-06 6:22 UTC (permalink / raw)
To: gdb-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=95e40d770e95c0d5317c2566a7976bd3421f380a
commit 95e40d770e95c0d5317c2566a7976bd3421f380a
Author: Mike Frysinger <vapier@gentoo.org>
Date: Mon Dec 6 02:42:00 2021 -0500
sim: ppc: migrate to standard uintXX_t types
Drop the sim-specific unsignedXX types and move to the standard uintXX_t
types that C11 provides.
Diff:
---
sim/ppc/altivec.igen | 404 +++++++-------
sim/ppc/altivec_registers.h | 8 +-
sim/ppc/bits.c | 24 +-
sim/ppc/bits.h | 32 +-
sim/ppc/corefile.c | 2 +-
sim/ppc/cpu.c | 14 +-
sim/ppc/cpu.h | 8 +-
sim/ppc/device.c | 6 +-
sim/ppc/device.h | 4 +-
sim/ppc/double.c | 16 +-
sim/ppc/e500.igen | 1274 +++++++++++++++++++++---------------------
sim/ppc/e500_expression.h | 24 +-
sim/ppc/e500_registers.h | 4 +-
sim/ppc/emul_chirp.c | 32 +-
sim/ppc/emul_generic.c | 12 +-
sim/ppc/emul_generic.h | 4 +-
sim/ppc/emul_unix.c | 154 ++---
sim/ppc/events.c | 22 +-
sim/ppc/events.h | 6 +-
sim/ppc/hw_disk.c | 12 +-
sim/ppc/hw_eeprom.c | 44 +-
sim/ppc/hw_htab.c | 66 +--
sim/ppc/hw_ide.c | 20 +-
sim/ppc/hw_nvram.c | 12 +-
sim/ppc/hw_opic.c | 4 +-
sim/ppc/hw_register.c | 2 +-
sim/ppc/hw_sem.c | 2 +-
sim/ppc/hw_trace.c | 2 +-
sim/ppc/idecode_expression.h | 44 +-
sim/ppc/pk_disklabel.c | 38 +-
sim/ppc/ppc-instructions | 308 +++++-----
sim/ppc/psim.c | 6 +-
sim/ppc/registers.c | 4 +-
sim/ppc/registers.h | 10 +-
sim/ppc/sim-main.h | 2 +-
sim/ppc/tree.c | 4 +-
sim/ppc/words.h | 45 +-
37 files changed, 1332 insertions(+), 1343 deletions(-)
diff --git a/sim/ppc/altivec.igen b/sim/ppc/altivec.igen
index c6b7f8164c3..63fe95a53d5 100644
--- a/sim/ppc/altivec.igen
+++ b/sim/ppc/altivec.igen
@@ -27,16 +27,16 @@
:cache:av:::VS:VS:
:cache:av::vreg *:vS:VS:(cpu_registers(processor)->altivec.vr + VS)
-:cache:av::unsigned32:VS_BITMASK:VS:(1 << VS)
+:cache:av::uint32_t:VS_BITMASK:VS:(1 << VS)
:cache:av:::VA:VA:
:cache:av::vreg *:vA:VA:(cpu_registers(processor)->altivec.vr + VA)
-:cache:av::unsigned32:VA_BITMASK:VA:(1 << VA)
+:cache:av::uint32_t:VA_BITMASK:VA:(1 << VA)
:cache:av:::VB:VB:
:cache:av::vreg *:vB:VB:(cpu_registers(processor)->altivec.vr + VB)
-:cache:av::unsigned32:VB_BITMASK:VB:(1 << VB)
+:cache:av::uint32_t:VB_BITMASK:VB:(1 << VB)
:cache:av:::VC:VC:
:cache:av::vreg *:vC:VC:(cpu_registers(processor)->altivec.vr + VC)
-:cache:av::unsigned32:VC_BITMASK:VC:(1 << VC)
+:cache:av::uint32_t:VC_BITMASK:VC:(1 << VC)
# Flags for model.h
::model-macro:::
@@ -77,7 +77,7 @@
} while (0)
# Trace waiting for AltiVec registers to become available
-void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, unsigned32 vr_busy
+void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, uint32_t vr_busy
int i;
if (vr_busy) {
vr_busy &= model_ptr->vr_busy;
@@ -91,7 +91,7 @@ void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, unsigned32
TRACE(trace_model, ("Waiting for VSCR\n"));
# Trace making AltiVec registers busy
-void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, unsigned32 vr_mask, unsigned32 cr_mask
+void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, uint32_t vr_mask, uint32_t cr_mask
int i;
if (vr_mask) {
for(i = 0; i < 32; i++) {
@@ -109,9 +109,9 @@ void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, unsigne
}
# Schedule an AltiVec instruction that takes integer input registers and produces output registers
-void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned32 out_vmask, const unsigned32 in_vmask
- const unsigned32 int_mask = out_mask | in_mask;
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const uint32_t out_vmask, const uint32_t in_vmask
+ const uint32_t int_mask = out_mask | in_mask;
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if ((model_ptr->int_busy & int_mask) != 0 || (model_ptr->vr_busy & vr_mask)) {
@@ -146,8 +146,8 @@ void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr,
}
# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers
-void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, const uint32_t out_vmask, const uint32_t in_vmask
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if (model_ptr->vr_busy & vr_mask) {
@@ -174,8 +174,8 @@ void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, con
}
# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches CR
-void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask, const unsigned32 cr_mask
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr, const uint32_t out_vmask, const uint32_t in_vmask, const uint32_t cr_mask
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if ((model_ptr->vr_busy & vr_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) {
@@ -208,8 +208,8 @@ void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr,
model_trace_altivec_make_busy(model_ptr, vr_mask, cr_mask);
# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches VSCR
-void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr, const uint32_t out_vmask, const uint32_t in_vmask
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) {
@@ -237,7 +237,7 @@ void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr
model_trace_altivec_make_busy(model_ptr, vr_mask, 0);
# Schedule an MFVSCR instruction that VSCR input register and produces an AltiVec output register
-void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask
+void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_ptr, const uint32_t vr_mask
model_busy *busy_ptr;
while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) {
@@ -259,7 +259,7 @@ void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_p
model_trace_altivec_make_busy(model_ptr, vr_mask, 0);
# Schedule an MTVSCR instruction that one AltiVec input register and produces a vscr output register
-void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask
+void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr, const uint32_t vr_mask
model_busy *busy_ptr;
while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) {
@@ -278,8 +278,8 @@ void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr
# The follow are AltiVec saturate operations
-signed8::model-function::altivec_signed_saturate_8:signed16 val, int *sat
- signed8 rv;
+int8_t::model-function::altivec_signed_saturate_8:int16_t val, int *sat
+ int8_t rv;
if (val > 127) {
rv = 127;
*sat = 1;
@@ -292,8 +292,8 @@ signed8::model-function::altivec_signed_saturate_8:signed16 val, int *sat
}
return rv;
-signed16::model-function::altivec_signed_saturate_16:signed32 val, int *sat
- signed16 rv;
+int16_t::model-function::altivec_signed_saturate_16:int32_t val, int *sat
+ int16_t rv;
if (val > 32767) {
rv = 32767;
*sat = 1;
@@ -306,8 +306,8 @@ signed16::model-function::altivec_signed_saturate_16:signed32 val, int *sat
}
return rv;
-signed32::model-function::altivec_signed_saturate_32:signed64 val, int *sat
- signed32 rv;
+int32_t::model-function::altivec_signed_saturate_32:int64_t val, int *sat
+ int32_t rv;
if (val > 2147483647) {
rv = 2147483647;
*sat = 1;
@@ -320,8 +320,8 @@ signed32::model-function::altivec_signed_saturate_32:signed64 val, int *sat
}
return rv;
-unsigned8::model-function::altivec_unsigned_saturate_8:signed16 val, int *sat
- unsigned8 rv;
+uint8_t::model-function::altivec_unsigned_saturate_8:int16_t val, int *sat
+ uint8_t rv;
if (val > 255) {
rv = 255;
*sat = 1;
@@ -334,8 +334,8 @@ unsigned8::model-function::altivec_unsigned_saturate_8:signed16 val, int *sat
}
return rv;
-unsigned16::model-function::altivec_unsigned_saturate_16:signed32 val, int *sat
- unsigned16 rv;
+uint16_t::model-function::altivec_unsigned_saturate_16:int32_t val, int *sat
+ uint16_t rv;
if (val > 65535) {
rv = 65535;
*sat = 1;
@@ -348,8 +348,8 @@ unsigned16::model-function::altivec_unsigned_saturate_16:signed32 val, int *sat
}
return rv;
-unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
- unsigned32 rv;
+uint32_t::model-function::altivec_unsigned_saturate_32:int64_t val, int *sat
+ uint32_t rv;
if (val > 4294967295LL) {
rv = 4294967295LL;
*sat = 1;
@@ -573,17 +573,17 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
#
0.4,6.VS,11.VA,16.VB,21.384:VX:av:vaddcuw %VD, %VA, %VB:Vector Add Carryout Unsigned Word
- unsigned64 temp;
+ uint64_t temp;
int i;
for (i = 0; i < 4; i++) {
- temp = (unsigned64)(*vA).w[i] + (unsigned64)(*vB).w[i];
+ temp = (uint64_t)(*vA).w[i] + (uint64_t)(*vB).w[i];
(*vS).w[i] = temp >> 32;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.10:VX:av:vaddfp %VD, %VA, %VB:Vector Add Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -596,9 +596,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.768:VX:av:vaddsbs %VD, %VA, %VB:Vector Add Signed Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
for (i = 0; i < 16; i++) {
- temp = (signed16)(signed8)(*vA).b[i] + (signed16)(signed8)(*vB).b[i];
+ temp = (int16_t)(int8_t)(*vA).b[i] + (int16_t)(int8_t)(*vB).b[i];
(*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -607,10 +607,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.832:VX:av:vaddshs %VD, %VA, %VB:Vector Add Signed Half Word Saturate
int i, sat, tempsat;
- signed32 temp, a, b;
+ int32_t temp, a, b;
for (i = 0; i < 8; i++) {
- a = (signed32)(signed16)(*vA).h[i];
- b = (signed32)(signed16)(*vB).h[i];
+ a = (int32_t)(int16_t)(*vA).h[i];
+ b = (int32_t)(int16_t)(*vB).h[i];
temp = a + b;
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
sat |= tempsat;
@@ -620,9 +620,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.896:VX:av:vaddsws %VD, %VA, %VB:Vector Add Signed Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (i = 0; i < 4; i++) {
- temp = (signed64)(signed32)(*vA).w[i] + (signed64)(signed32)(*vB).w[i];
+ temp = (int64_t)(int32_t)(*vA).w[i] + (int64_t)(int32_t)(*vB).w[i];
(*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -637,10 +637,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.512:VX:av:vaddubs %VD, %VA, %VB:Vector Add Unsigned Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
- temp = (signed16)(unsigned8)(*vA).b[i] + (signed16)(unsigned8)(*vB).b[i];
+ temp = (int16_t)(uint8_t)(*vA).b[i] + (int16_t)(uint8_t)(*vB).b[i];
(*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -655,9 +655,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.576:VX:av:vadduhs %VD, %VA, %VB:Vector Add Unsigned Half Word Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
for (i = 0; i < 8; i++) {
- temp = (signed32)(unsigned16)(*vA).h[i] + (signed32)(unsigned16)(*vB).h[i];
+ temp = (int32_t)(uint16_t)(*vA).h[i] + (int32_t)(uint16_t)(*vB).h[i];
(*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat);
sat |= tempsat;
}
@@ -672,9 +672,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.640:VX:av:vadduws %VD, %VA, %VB:Vector Add Unsigned Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (i = 0; i < 4; i++) {
- temp = (signed64)(unsigned32)(*vA).w[i] + (signed64)(unsigned32)(*vB).w[i];
+ temp = (int64_t)(uint32_t)(*vA).w[i] + (int64_t)(uint32_t)(*vB).w[i];
(*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -704,10 +704,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1282:VX:av:vavgsb %VD, %VA, %VB:Vector Average Signed Byte
int i;
- signed16 temp, a, b;
+ int16_t temp, a, b;
for (i = 0; i < 16; i++) {
- a = (signed16)(signed8)(*vA).b[i];
- b = (signed16)(signed8)(*vB).b[i];
+ a = (int16_t)(int8_t)(*vA).b[i];
+ b = (int16_t)(int8_t)(*vB).b[i];
temp = a + b + 1;
(*vS).b[i] = (temp >> 1) & 0xff;
}
@@ -715,10 +715,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1346:VX:av:vavgsh %VD, %VA, %VB:Vector Average Signed Half Word
int i;
- signed32 temp, a, b;
+ int32_t temp, a, b;
for (i = 0; i < 8; i++) {
- a = (signed32)(signed16)(*vA).h[i];
- b = (signed32)(signed16)(*vB).h[i];
+ a = (int32_t)(int16_t)(*vA).h[i];
+ b = (int32_t)(int16_t)(*vB).h[i];
temp = a + b + 1;
(*vS).h[i] = (temp >> 1) & 0xffff;
}
@@ -726,10 +726,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1410:VX:av:vavgsw %VD, %VA, %VB:Vector Average Signed Word
int i;
- signed64 temp, a, b;
+ int64_t temp, a, b;
for (i = 0; i < 4; i++) {
- a = (signed64)(signed32)(*vA).w[i];
- b = (signed64)(signed32)(*vB).w[i];
+ a = (int64_t)(int32_t)(*vA).w[i];
+ b = (int64_t)(int32_t)(*vB).w[i];
temp = a + b + 1;
(*vS).w[i] = (temp >> 1) & 0xffffffff;
}
@@ -737,7 +737,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1026:VX:av:vavgub %VD, %VA, %VB:Vector Average Unsigned Byte
int i;
- unsigned16 temp, a, b;
+ uint16_t temp, a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -748,7 +748,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1090:VX:av:vavguh %VD, %VA, %VB:Vector Average Unsigned Half Word
int i;
- unsigned32 temp, a, b;
+ uint32_t temp, a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -759,7 +759,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1154:VX:av:vavguw %VD, %VA, %VB:Vector Average Unsigned Word
int i;
- unsigned64 temp, a, b;
+ uint64_t temp, a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -774,7 +774,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.842:VX:av:vcfsx %VD, %VB, %UIMM:Vector Convert From Signed Fixed-Point Word
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu b, div, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&b, (*vB).w[i]);
@@ -787,7 +787,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.778:VX:av:vcfux %VD, %VA, %UIMM:Vector Convert From Unsigned Fixed-Point Word
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu b, d, div;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&b, (*vB).w[i]);
@@ -896,7 +896,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.774:VXR:av:vcmpgtsbx %VD, %VA, %VB:Vector Compare Greater-Than Signed Byte
int i;
- signed8 a, b;
+ int8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -911,7 +911,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.838:VXR:av:vcmpgtshx %VD, %VA, %VB:Vector Compare Greater-Than Signed Half Word
int i;
- signed16 a, b;
+ int16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -926,7 +926,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.902:VXR:av:vcmpgtswx %VD, %VA, %VB:Vector Compare Greater-Than Signed Word
int i;
- signed32 a, b;
+ int32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -941,7 +941,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.518:VXR:av:vcmpgtubx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Byte
int i;
- unsigned8 a, b;
+ uint8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -956,7 +956,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.582:VXR:av:vcmpgtuhx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Half Word
int i;
- unsigned16 a, b;
+ uint16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -971,7 +971,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.646:VXR:av:vcmpgtuwx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Word
int i;
- unsigned32 a, b;
+ uint32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -990,7 +990,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.970:VX:av:vctsxs %VD, %VB, %UIMM:Vector Convert to Signed Fixed-Point Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
sim_fpu a, b, m;
sat = 0;
for (i = 0; i < 4; i++) {
@@ -1006,7 +1006,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.906:VX:av:vctuxs %VD, %VB, %UIMM:Vector Convert to Unsigned Fixed-Point Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
sim_fpu a, b, m;
sat = 0;
for (i = 0; i < 4; i++) {
@@ -1026,8 +1026,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.394:VX:av:vexptefp %VD, %VB:Vector 2 Raised to the Exponent Estimate Floating Point
int i;
- unsigned32 f;
- signed32 bi;
+ uint32_t f;
+ int32_t bi;
sim_fpu b, d;
for (i = 0; i < 4; i++) {
/*HACK!*/
@@ -1042,7 +1042,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.458:VX:av:vlogefp %VD, %VB:Vector Log2 Estimate Floating Point
int i;
- unsigned32 c, u, f;
+ uint32_t c, u, f;
sim_fpu b, cfpu, d;
for (i = 0; i < 4; i++) {
/*HACK!*/
@@ -1063,7 +1063,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.46:VAX:av:vmaddfp %VD, %VA, %VB, %VC:Vector Multiply Add Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, c, d, e;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1083,7 +1083,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1034:VX:av:vmaxfp %VD, %VA, %VB:Vector Maximum Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1096,7 +1096,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.258:VX:av:vmaxsb %VD, %VA, %VB:Vector Maximum Signed Byte
int i;
- signed8 a, b;
+ int8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1109,7 +1109,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.322:VX:av:vmaxsh %VD, %VA, %VB:Vector Maximum Signed Half Word
int i;
- signed16 a, b;
+ int16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1122,7 +1122,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.386:VX:av:vmaxsw %VD, %VA, %VB:Vector Maximum Signed Word
int i;
- signed32 a, b;
+ int32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1135,7 +1135,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.2:VX:av:vmaxub %VD, %VA, %VB:Vector Maximum Unsigned Byte
int i;
- unsigned8 a, b;
+ uint8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1148,7 +1148,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.66:VX:av:vmaxus %VD, %VA, %VB:Vector Maximum Unsigned Half Word
int i;
- unsigned16 a, b;
+ uint16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1161,7 +1161,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.130:VX:av:vmaxuw %VD, %VA, %VB:Vector Maximum Unsigned Word
int i;
- unsigned32 a, b;
+ uint32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1179,13 +1179,13 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.32:VAX:av:vmhaddshs %VD, %VA, %VB, %VC:Vector Multiple High and Add Signed Half Word Saturate
int i, sat, tempsat;
- signed16 a, b;
- signed32 prod, temp, c;
+ int16_t a, b;
+ int32_t prod, temp, c;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
- c = (signed32)(signed16)(*vC).h[i];
- prod = (signed32)a * (signed32)b;
+ c = (int32_t)(int16_t)(*vC).h[i];
+ prod = (int32_t)a * (int32_t)b;
temp = (prod >> 15) + c;
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
sat |= tempsat;
@@ -1195,13 +1195,13 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.33:VAX:av:vmhraddshs %VD, %VA, %VB, %VC:Vector Multiple High Round and Add Signed Half Word Saturate
int i, sat, tempsat;
- signed16 a, b;
- signed32 prod, temp, c;
+ int16_t a, b;
+ int32_t prod, temp, c;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
- c = (signed32)(signed16)(*vC).h[i];
- prod = (signed32)a * (signed32)b;
+ c = (int32_t)(int16_t)(*vC).h[i];
+ prod = (int32_t)a * (int32_t)b;
prod += 0x4000;
temp = (prod >> 15) + c;
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
@@ -1217,7 +1217,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1098:VX:av:vminfp %VD, %VA, %VB:Vector Minimum Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1230,7 +1230,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.770:VX:av:vminsb %VD, %VA, %VB:Vector Minimum Signed Byte
int i;
- signed8 a, b;
+ int8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1243,7 +1243,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.834:VX:av:vminsh %VD, %VA, %VB:Vector Minimum Signed Half Word
int i;
- signed16 a, b;
+ int16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1256,7 +1256,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.898:VX:av:vminsw %VD, %VA, %VB:Vector Minimum Signed Word
int i;
- signed32 a, b;
+ int32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1269,7 +1269,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.514:VX:av:vminub %VD, %VA, %VB:Vector Minimum Unsigned Byte
int i;
- unsigned8 a, b;
+ uint8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1282,7 +1282,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.578:VX:av:vminuh %VD, %VA, %VB:Vector Minimum Unsigned Half Word
int i;
- unsigned16 a, b;
+ uint16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1295,7 +1295,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.642:VX:av:vminuw %VD, %VA, %VB:Vector Minimum Unsigned Word
int i;
- unsigned32 a, b;
+ uint32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1313,13 +1313,13 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.34:VAX:av:vmladduhm %VD, %VA, %VB, %VC:Vector Multiply Low and Add Unsigned Half Word Modulo
int i;
- unsigned16 a, b, c;
- unsigned32 prod;
+ uint16_t a, b, c;
+ uint32_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
c = (*vC).h[i];
- prod = (unsigned32)a * (unsigned32)b;
+ prod = (uint32_t)a * (uint32_t)b;
(*vS).h[i] = (prod + c) & 0xffff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);
@@ -1384,16 +1384,16 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.37:VAX:av:vmsummbm %VD, %VA, %VB, %VC:Vector Multiply Sum Mixed-Sign Byte Modulo
int i, j;
- signed32 temp;
- signed16 prod, a;
- unsigned16 b;
+ int32_t temp;
+ int16_t prod, a;
+ uint16_t b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 4; j++) {
- a = (signed16)(signed8)(*vA).b[i*4+j];
+ a = (int16_t)(int8_t)(*vA).b[i*4+j];
b = (*vB).b[i*4+j];
prod = a * b;
- temp += (signed32)prod;
+ temp += (int32_t)prod;
}
(*vS).w[i] = temp;
}
@@ -1401,12 +1401,12 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.40:VAX:av:vmsumshm %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Modulo
int i, j;
- signed32 temp, prod, a, b;
+ int32_t temp, prod, a, b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 2; j++) {
- a = (signed32)(signed16)(*vA).h[i*2+j];
- b = (signed32)(signed16)(*vB).h[i*2+j];
+ a = (int32_t)(int16_t)(*vA).h[i*2+j];
+ b = (int32_t)(int16_t)(*vB).h[i*2+j];
prod = a * b;
temp += prod;
}
@@ -1416,16 +1416,16 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.41:VAX:av:vmsumshs %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Saturate
int i, j, sat, tempsat;
- signed64 temp;
- signed32 prod, a, b;
+ int64_t temp;
+ int32_t prod, a, b;
sat = 0;
for (i = 0; i < 4; i++) {
- temp = (signed64)(signed32)(*vC).w[i];
+ temp = (int64_t)(int32_t)(*vC).w[i];
for (j = 0; j < 2; j++) {
- a = (signed32)(signed16)(*vA).h[i*2+j];
- b = (signed32)(signed16)(*vB).h[i*2+j];
+ a = (int32_t)(int16_t)(*vA).h[i*2+j];
+ b = (int32_t)(int16_t)(*vB).h[i*2+j];
prod = a * b;
- temp += (signed64)prod;
+ temp += (int64_t)prod;
}
(*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
@@ -1435,8 +1435,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.36:VAX:av:vmsumubm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Byte Modulo
int i, j;
- unsigned32 temp;
- unsigned16 prod, a, b;
+ uint32_t temp;
+ uint16_t prod, a, b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 4; j++) {
@@ -1451,7 +1451,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.38:VAX:av:vmsumuhm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Modulo
int i, j;
- unsigned32 temp, prod, a, b;
+ uint32_t temp, prod, a, b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 2; j++) {
@@ -1466,7 +1466,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.39:VAX:av:vmsumuhs %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Saturate
int i, j, sat, tempsat;
- unsigned32 temp, prod, a, b;
+ uint32_t temp, prod, a, b;
sat = 0;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
@@ -1489,8 +1489,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.776:VX:av:vmulesb %VD, %VA, %VB:Vector Multiply Even Signed Byte
int i;
- signed8 a, b;
- signed16 prod;
+ int8_t a, b;
+ int16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX(i*2)];
b = (*vB).b[AV_BINDEX(i*2)];
@@ -1501,8 +1501,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.840:VX:av:vmulesh %VD, %VA, %VB:Vector Multiply Even Signed Half Word
int i;
- signed16 a, b;
- signed32 prod;
+ int16_t a, b;
+ int32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX(i*2)];
b = (*vB).h[AV_HINDEX(i*2)];
@@ -1513,8 +1513,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.520:VX:av:vmuleub %VD, %VA, %VB:Vector Multiply Even Unsigned Byte
int i;
- unsigned8 a, b;
- unsigned16 prod;
+ uint8_t a, b;
+ uint16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX(i*2)];
b = (*vB).b[AV_BINDEX(i*2)];
@@ -1525,8 +1525,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.584:VX:av:vmuleuh %VD, %VA, %VB:Vector Multiply Even Unsigned Half Word
int i;
- unsigned16 a, b;
- unsigned32 prod;
+ uint16_t a, b;
+ uint32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX(i*2)];
b = (*vB).h[AV_HINDEX(i*2)];
@@ -1537,8 +1537,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.264:VX:av:vmulosb %VD, %VA, %VB:Vector Multiply Odd Signed Byte
int i;
- signed8 a, b;
- signed16 prod;
+ int8_t a, b;
+ int16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX((i*2)+1)];
b = (*vB).b[AV_BINDEX((i*2)+1)];
@@ -1549,8 +1549,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.328:VX:av:vmulosh %VD, %VA, %VB:Vector Multiply Odd Signed Half Word
int i;
- signed16 a, b;
- signed32 prod;
+ int16_t a, b;
+ int32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX((i*2)+1)];
b = (*vB).h[AV_HINDEX((i*2)+1)];
@@ -1561,8 +1561,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.8:VX:av:vmuloub %VD, %VA, %VB:Vector Multiply Odd Unsigned Byte
int i;
- unsigned8 a, b;
- unsigned16 prod;
+ uint8_t a, b;
+ uint16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX((i*2)+1)];
b = (*vB).b[AV_BINDEX((i*2)+1)];
@@ -1573,8 +1573,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.72:VX:av:vmulouh %VD, %VA, %VB:Vector Multiply Odd Unsigned Half Word
int i;
- unsigned16 a, b;
- unsigned32 prod;
+ uint16_t a, b;
+ uint32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX((i*2)+1)];
b = (*vB).h[AV_HINDEX((i*2)+1)];
@@ -1590,7 +1590,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.47:VX:av:vnmsubfp %VD, %VA, %VB, %VC:Vector Negative Multiply-Subtract Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, c, d, i1, i2;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1667,7 +1667,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.398:VX:av:vpkshss %VD, %VA, %VB:Vector Pack Signed Half Word Signed Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
if (i < 8)
@@ -1682,7 +1682,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.270:VX:av:vpkshus %VD, %VA, %VB:Vector Pack Signed Half Word Unsigned Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
if (i < 8)
@@ -1697,7 +1697,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.462:VX:av:vpkswss %VD, %VA, %VB:Vector Pack Signed Word Signed Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
if (i < 4)
@@ -1712,7 +1712,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.334:VX:av:vpkswus %VD, %VA, %VB:Vector Pack Signed Word Unsigned Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
if (i < 4)
@@ -1736,14 +1736,14 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.142:VX:av:vpkuhus %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
if (i < 8)
temp = (*vA).h[AV_HINDEX(i)];
else
temp = (*vB).h[AV_HINDEX(i-8)];
- /* force positive in signed16, ok as we'll toss the bit away anyway */
+ /* force positive in int16_t, ok as we'll toss the bit away anyway */
temp &= ~0x8000;
(*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat);
sat |= tempsat;
@@ -1762,14 +1762,14 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.206:VX:av:vpkuwus %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
if (i < 4)
temp = (*vA).w[i];
else
temp = (*vB).w[i-4];
- /* force positive in signed32, ok as we'll toss the bit away anyway */
+ /* force positive in int32_t, ok as we'll toss the bit away anyway */
temp &= ~0x80000000;
(*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat);
sat |= tempsat;
@@ -1784,7 +1784,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.266:VX:av:vrefp %VD, %VB:Vector Reciprocal Estimate Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1796,7 +1796,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.330:VX:av:vrsqrtefp %VD, %VB:Vector Reciprocal Square Root Estimate Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op, i1, one, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1814,7 +1814,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.714:VX:av:vrfim %VD, %VB:Vector Round to Floating-Point Integer towards Minus Infinity
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1826,7 +1826,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.522:VX:av:vrfin %VD, %VB:Vector Round to Floating-Point Integer Nearest
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1838,7 +1838,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.650:VX:av:vrfip %VD, %VB:Vector Round to Floating-Point Integer towards Plus Infinity
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1850,7 +1850,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.586:VX:av:vrfiz %VD, %VB:Vector Round to Floating-Point Integer towards Zero
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1867,27 +1867,27 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.4:VX:av:vrlb %VD, %VA, %VB:Vector Rotate Left Integer Byte
int i;
- unsigned16 temp;
+ uint16_t temp;
for (i = 0; i < 16; i++) {
- temp = (unsigned16)(*vA).b[i] << (((*vB).b[i]) & 7);
+ temp = (uint16_t)(*vA).b[i] << (((*vB).b[i]) & 7);
(*vS).b[i] = (temp & 0xff) | ((temp >> 8) & 0xff);
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.68:VX:av:vrlh %VD, %VA, %VB:Vector Rotate Left Integer Half Word
int i;
- unsigned32 temp;
+ uint32_t temp;
for (i = 0; i < 8; i++) {
- temp = (unsigned32)(*vA).h[i] << (((*vB).h[i]) & 0xf);
+ temp = (uint32_t)(*vA).h[i] << (((*vB).h[i]) & 0xf);
(*vS).h[i] = (temp & 0xffff) | ((temp >> 16) & 0xffff);
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.132:VX:av:vrlw %VD, %VA, %VB:Vector Rotate Left Integer Word
int i;
- unsigned64 temp;
+ uint64_t temp;
for (i = 0; i < 4; i++) {
- temp = (unsigned64)(*vA).w[i] << (((*vB).w[i]) & 0x1f);
+ temp = (uint64_t)(*vA).w[i] << (((*vB).w[i]) & 0x1f);
(*vS).w[i] = (temp & 0xffffffff) | ((temp >> 32) & 0xffffffff);
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
@@ -1899,7 +1899,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.42:VAX:av:vsel %VD, %VA, %VB, %VC:Vector Conditional Select
int i;
- unsigned32 c;
+ uint32_t c;
for (i = 0; i < 4; i++) {
c = (*vC).w[i];
(*vS).w[i] = ((*vB).w[i] & c) | ((*vA).w[i] & ~c);
@@ -1978,7 +1978,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.524:VX:av:vspltb %VD, %VB, %UIMM:Vector Splat Byte
int i;
- unsigned8 b;
+ uint8_t b;
b = (*vB).b[AV_BINDEX(UIMM & 0xf)];
for (i = 0; i < 16; i++)
(*vS).b[i] = b;
@@ -1986,7 +1986,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.588:VX:av:vsplth %VD, %VB, %UIMM:Vector Splat Half Word
int i;
- unsigned16 h;
+ uint16_t h;
h = (*vB).h[AV_HINDEX(UIMM & 0x7)];
for (i = 0; i < 8; i++)
(*vS).h[i] = h;
@@ -1994,7 +1994,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.SIMM,16.0,21.780:VX:av:vspltisb %VD, %SIMM:Vector Splat Immediate Signed Byte
int i;
- signed8 b = SIMM;
+ int8_t b = SIMM;
/* manual 5-bit signed extension */
if (b & 0x10)
b -= 0x20;
@@ -2004,7 +2004,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.SIMM,16.0,21.844:VX:av:vspltish %VD, %SIMM:Vector Splat Immediate Signed Half Word
int i;
- signed16 h = SIMM;
+ int16_t h = SIMM;
/* manual 5-bit signed extension */
if (h & 0x10)
h -= 0x20;
@@ -2014,7 +2014,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.SIMM,16.0,21.908:VX:av:vspltisw %VD, %SIMM:Vector Splat Immediate Signed Word
int i;
- signed32 w = SIMM;
+ int32_t w = SIMM;
/* manual 5-bit signed extension */
if (w & 0x10)
w -= 0x20;
@@ -2024,7 +2024,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.652:VX:av:vspltw %VD, %VB, %UIMM:Vector Splat Word
int i;
- unsigned32 w;
+ uint32_t w;
w = (*vB).w[UIMM & 0x3];
for (i = 0; i < 4; i++)
(*vS).w[i] = w;
@@ -2052,30 +2052,30 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.772:VX:av:vsrab %VD, %VA, %VB:Vector Shift Right Algebraic Byte
int i, sh;
- signed16 a;
+ int16_t a;
for (i = 0; i < 16; i++) {
sh = ((*vB).b[i]) & 7;
- a = (signed16)(signed8)(*vA).b[i];
+ a = (int16_t)(int8_t)(*vA).b[i];
(*vS).b[i] = (a >> sh) & 0xff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.836:VX:av:vsrah %VD, %VA, %VB:Vector Shift Right Algebraic Half Word
int i, sh;
- signed32 a;
+ int32_t a;
for (i = 0; i < 8; i++) {
sh = ((*vB).h[i]) & 0xf;
- a = (signed32)(signed16)(*vA).h[i];
+ a = (int32_t)(int16_t)(*vA).h[i];
(*vS).h[i] = (a >> sh) & 0xffff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.900:VX:av:vsraw %VD, %VA, %VB:Vector Shift Right Algebraic Word
int i, sh;
- signed64 a;
+ int64_t a;
for (i = 0; i < 4; i++) {
sh = ((*vB).w[i]) & 0xf;
- a = (signed64)(signed32)(*vA).w[i];
+ a = (int64_t)(int32_t)(*vA).w[i];
(*vS).w[i] = (a >> sh) & 0xffffffff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
@@ -2125,10 +2125,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1408:VX:av:vsubcuw %VD, %VA, %VB:Vector Subtract Carryout Unsigned Word
int i;
- signed64 temp, a, b;
+ int64_t temp, a, b;
for (i = 0; i < 4; i++) {
- a = (signed64)(unsigned32)(*vA).w[i];
- b = (signed64)(unsigned32)(*vB).w[i];
+ a = (int64_t)(uint32_t)(*vA).w[i];
+ b = (int64_t)(uint32_t)(*vB).w[i];
temp = a - b;
(*vS).w[i] = ~(temp >> 32) & 1;
}
@@ -2136,7 +2136,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.74:VX:av:vsubfp %VD, %VA, %VB:Vector Subtract Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -2149,10 +2149,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1792:VX:av:vsubsbs %VD, %VA, %VB:Vector Subtract Signed Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
- temp = (signed16)(signed8)(*vA).b[i] - (signed16)(signed8)(*vB).b[i];
+ temp = (int16_t)(int8_t)(*vA).b[i] - (int16_t)(int8_t)(*vB).b[i];
(*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -2161,10 +2161,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1856:VX:av:vsubshs %VD, %VA, %VB:Vector Subtract Signed Half Word Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
- temp = (signed32)(signed16)(*vA).h[i] - (signed32)(signed16)(*vB).h[i];
+ temp = (int32_t)(int16_t)(*vA).h[i] - (int32_t)(int16_t)(*vB).h[i];
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
sat |= tempsat;
}
@@ -2173,10 +2173,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1920:VX:av:vsubsws %VD, %VA, %VB:Vector Subtract Signed Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
sat = 0;
for (i = 0; i < 4; i++) {
- temp = (signed64)(signed32)(*vA).w[i] - (signed64)(signed32)(*vB).w[i];
+ temp = (int64_t)(int32_t)(*vA).w[i] - (int64_t)(int32_t)(*vB).w[i];
(*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2191,10 +2191,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1536:VX:av:vsububs %VD, %VA, %VB:Vector Subtract Unsigned Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
- temp = (signed16)(unsigned8)(*vA).b[i] - (signed16)(unsigned8)(*vB).b[i];
+ temp = (int16_t)(uint8_t)(*vA).b[i] - (int16_t)(uint8_t)(*vB).b[i];
(*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -2209,9 +2209,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1600:VX:av:vsubuhs %VD, %VA, %VB:Vector Subtract Unsigned Half Word Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
for (i = 0; i < 8; i++) {
- temp = (signed32)(unsigned16)(*vA).h[i] - (signed32)(unsigned16)(*vB).h[i];
+ temp = (int32_t)(uint16_t)(*vA).h[i] - (int32_t)(uint16_t)(*vB).h[i];
(*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat);
sat |= tempsat;
}
@@ -2226,9 +2226,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1664:VX:av:vsubuws %VD, %VA, %VB:Vector Subtract Unsigned Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (i = 0; i < 4; i++) {
- temp = (signed64)(unsigned32)(*vA).w[i] - (signed64)(unsigned32)(*vB).w[i];
+ temp = (int64_t)(uint32_t)(*vA).w[i] - (int64_t)(uint32_t)(*vB).w[i];
(*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2242,10 +2242,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1928:VX:av:vsumsws %VD, %VA, %VB:Vector Sum Across Signed Word Saturate
int i, sat;
- signed64 temp;
- temp = (signed64)(signed32)(*vB).w[3];
+ int64_t temp;
+ temp = (int64_t)(int32_t)(*vB).w[3];
for (i = 0; i < 4; i++)
- temp += (signed64)(signed32)(*vA).w[i];
+ temp += (int64_t)(int32_t)(*vA).w[i];
(*vS).w[3] = altivec_signed_saturate_32(temp, &sat);
(*vS).w[0] = (*vS).w[1] = (*vS).w[2] = 0;
ALTIVEC_SET_SAT(sat);
@@ -2253,10 +2253,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1672:VX:av:vsum2sws %VD, %VA, %VB:Vector Sum Across Partial (1/2) Signed Word Saturate
int i, j, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (j = 0; j < 4; j += 2) {
- temp = (signed64)(signed32)(*vB).w[j+1];
- temp += (signed64)(signed32)(*vA).w[j] + (signed64)(signed32)(*vA).w[j+1];
+ temp = (int64_t)(int32_t)(*vB).w[j+1];
+ temp += (int64_t)(int32_t)(*vA).w[j] + (int64_t)(int32_t)(*vA).w[j+1];
(*vS).w[j+1] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2266,11 +2266,11 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1800:VX:av:vsum4sbs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Byte Saturate
int i, j, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (j = 0; j < 4; j++) {
- temp = (signed64)(signed32)(*vB).w[j];
+ temp = (int64_t)(int32_t)(*vB).w[j];
for (i = 0; i < 4; i++)
- temp += (signed64)(signed8)(*vA).b[i+(j*4)];
+ temp += (int64_t)(int8_t)(*vA).b[i+(j*4)];
(*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2279,11 +2279,11 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1608:VX:av:vsum4shs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Half Word Saturate
int i, j, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (j = 0; j < 4; j++) {
- temp = (signed64)(signed32)(*vB).w[j];
+ temp = (int64_t)(int32_t)(*vB).w[j];
for (i = 0; i < 2; i++)
- temp += (signed64)(signed16)(*vA).h[i+(j*2)];
+ temp += (int64_t)(int16_t)(*vA).h[i+(j*2)];
(*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2292,12 +2292,12 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1544:VX:av:vsum4ubs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Unsigned Byte Saturate
int i, j, sat, tempsat;
- signed64 utemp;
- signed64 temp;
+ int64_t utemp;
+ int64_t temp;
for (j = 0; j < 4; j++) {
- utemp = (signed64)(unsigned32)(*vB).w[j];
+ utemp = (int64_t)(uint32_t)(*vB).w[j];
for (i = 0; i < 4; i++)
- utemp += (signed64)(unsigned16)(*vA).b[i+(j*4)];
+ utemp += (int64_t)(uint16_t)(*vA).b[i+(j*4)];
temp = utemp;
(*vS).w[j] = altivec_unsigned_saturate_32(temp, &tempsat);
sat |= tempsat;
@@ -2312,7 +2312,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.846:VX:av:vupkhpx %VD, %VB:Vector Unpack High Pixel16
int i;
- unsigned16 h;
+ uint16_t h;
for (i = 0; i < 4; i++) {
h = (*vB).h[AV_HINDEX(i)];
(*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0)
@@ -2325,18 +2325,18 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.526:VX:av:vupkhsb %VD, %VB:Vector Unpack High Signed Byte
int i;
for (i = 0; i < 8; i++)
- (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i)];
+ (*vS).h[AV_HINDEX(i)] = (int16_t)(int8_t)(*vB).b[AV_BINDEX(i)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
0.4,6.VS,11.0,16.VB,21.590:VX:av:vupkhsh %VD, %VB:Vector Unpack High Signed Half Word
int i;
for (i = 0; i < 4; i++)
- (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i)];
+ (*vS).w[i] = (int32_t)(int16_t)(*vB).h[AV_HINDEX(i)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
0.4,6.VS,11.0,16.VB,21.974:VX:av:vupklpx %VD, %VB:Vector Unpack Low Pixel16
int i;
- unsigned16 h;
+ uint16_t h;
for (i = 0; i < 4; i++) {
h = (*vB).h[AV_HINDEX(i + 4)];
(*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0)
@@ -2349,11 +2349,11 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.654:VX:av:vupklsb %VD, %VB:Vector Unpack Low Signed Byte
int i;
for (i = 0; i < 8; i++)
- (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i + 8)];
+ (*vS).h[AV_HINDEX(i)] = (int16_t)(int8_t)(*vB).b[AV_BINDEX(i + 8)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
0.4,6.VS,11.0,16.VB,21.718:VX:av:vupklsh %VD, %VB:Vector Unpack Low Signed Half Word
int i;
for (i = 0; i < 4; i++)
- (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i + 4)];
+ (*vS).w[i] = (int32_t)(int16_t)(*vB).h[AV_HINDEX(i + 4)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
diff --git a/sim/ppc/altivec_registers.h b/sim/ppc/altivec_registers.h
index 33480ed4fa4..8e6a2db8ecc 100644
--- a/sim/ppc/altivec_registers.h
+++ b/sim/ppc/altivec_registers.h
@@ -24,12 +24,12 @@
entities. */
typedef union
{
- unsigned8 b[16];
- unsigned16 h[8];
- unsigned32 w[4];
+ uint8_t b[16];
+ uint16_t h[8];
+ uint32_t w[4];
} vreg;
-typedef unsigned32 vscreg;
+typedef uint32_t vscreg;
struct altivec_regs {
/* AltiVec Registers */
diff --git a/sim/ppc/bits.c b/sim/ppc/bits.c
index 767f196fad5..bf2f8f0d6e9 100644
--- a/sim/ppc/bits.c
+++ b/sim/ppc/bits.c
@@ -24,8 +24,8 @@
#include "basics.h"
INLINE_BITS\
-(unsigned64)
-LSMASKED64 (unsigned64 word,
+(uint64_t)
+LSMASKED64 (uint64_t word,
int start,
int stop)
{
@@ -34,8 +34,8 @@ LSMASKED64 (unsigned64 word,
}
INLINE_BITS\
-(unsigned64)
-LSEXTRACTED64 (unsigned64 val,
+(uint64_t)
+LSEXTRACTED64 (uint64_t val,
int start,
int stop)
{
@@ -45,8 +45,8 @@ LSEXTRACTED64 (unsigned64 val,
}
INLINE_BITS\
-(unsigned32)
-MASKED32(unsigned32 word,
+(uint32_t)
+MASKED32(uint32_t word,
unsigned start,
unsigned stop)
{
@@ -54,8 +54,8 @@ MASKED32(unsigned32 word,
}
INLINE_BITS\
-(unsigned64)
-MASKED64(unsigned64 word,
+(uint64_t)
+MASKED64(uint64_t word,
unsigned start,
unsigned stop)
{
@@ -112,8 +112,8 @@ INSERTED(unsigned_word word,
INLINE_BITS\
-(unsigned32)
-ROTL32(unsigned32 val,
+(uint32_t)
+ROTL32(uint32_t val,
long shift)
{
ASSERT(shift >= 0 && shift <= 32);
@@ -122,8 +122,8 @@ ROTL32(unsigned32 val,
INLINE_BITS\
-(unsigned64)
-ROTL64(unsigned64 val,
+(uint64_t)
+ROTL64(uint64_t val,
long shift)
{
ASSERT(shift >= 0 && shift <= 64);
diff --git a/sim/ppc/bits.h b/sim/ppc/bits.h
index d3b765addb5..d08f8d59e64 100644
--- a/sim/ppc/bits.h
+++ b/sim/ppc/bits.h
@@ -108,7 +108,7 @@
/* multi bit mask */
#define _MASKn(WIDTH, START, STOP) \
-(((((unsigned##WIDTH)0) - 1) \
+(((((uint##WIDTH##_t)0) - 1) \
>> (WIDTH - ((STOP) - (START) + 1))) \
<< (WIDTH - 1 - (STOP)))
@@ -151,14 +151,14 @@
/* mask the required bits, leaving them in place */
INLINE_BITS\
-(unsigned32) MASKED32
-(unsigned32 word,
+(uint32_t) MASKED32
+(uint32_t word,
unsigned start,
unsigned stop);
INLINE_BITS\
-(unsigned64) MASKED64
-(unsigned64 word,
+(uint64_t) MASKED64
+(uint64_t word,
unsigned start,
unsigned stop);
@@ -169,8 +169,8 @@ INLINE_BITS\
unsigned stop);
INLINE_BITS\
-(unsigned64) LSMASKED64
-(unsigned64 word,
+(uint64_t) LSMASKED64
+(uint64_t word,
int first,
int last);
@@ -191,8 +191,8 @@ INLINE_BITS\
unsigned stop);
INLINE_BITS\
-(unsigned64) LSEXTRACTED64
-(unsigned64 val,
+(uint64_t) LSEXTRACTED64
+(uint64_t val,
int start,
int stop);
@@ -200,10 +200,10 @@ INLINE_BITS\
/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
- ? (((unsigned##N)(WORD) \
+ ? (((uint##N##_t)(WORD) \
>> (((NEW) > (OLD)) ? ((NEW) - (OLD)) : 0)) \
& MASK32((NEW), (NEW))) \
- : (((unsigned##N)(WORD) \
+ : (((uint##N##_t)(WORD) \
<< (((OLD) > (NEW)) ? ((OLD) - (NEW)) : 0)) \
& MASK32((NEW), (NEW))))
@@ -229,7 +229,7 @@ INLINE_BITS\
/* depending on MODE return a 64bit or 32bit (sign extended) value */
#if (WITH_TARGET_WORD_BITSIZE == 64)
-#define EXTENDED(X) ((signed64)(signed32)(X))
+#define EXTENDED(X) ((int64_t)(int32_t)(X))
#else
#define EXTENDED(X) (X)
#endif
@@ -270,13 +270,13 @@ do { \
(((VAL) << (SHIFT)) | ((VAL) >> ((N)-(SHIFT))))
INLINE_BITS\
-(unsigned32) ROTL32
-(unsigned32 val,
+(uint32_t) ROTL32
+(uint32_t val,
long shift);
INLINE_BITS\
-(unsigned64) ROTL64
-(unsigned64 val,
+(uint64_t) ROTL64
+(uint64_t val,
long shift);
diff --git a/sim/ppc/corefile.c b/sim/ppc/corefile.c
index ac8aa5d7e22..1b3eeef8b53 100644
--- a/sim/ppc/corefile.c
+++ b/sim/ppc/corefile.c
@@ -227,7 +227,7 @@ core_attach(core *memory,
if (attach == attach_raw_memory) {
/* Padd out the raw buffer to ensure that ADDR starts on a
correctly aligned boundary */
- int padding = (addr % sizeof (unsigned64));
+ int padding = (addr % sizeof (uint64_t));
free_buffer = zalloc(nr_bytes + padding);
buffer = (char*)free_buffer + padding;
}
diff --git a/sim/ppc/cpu.c b/sim/ppc/cpu.c
index 1462766e5fe..b89be03648b 100644
--- a/sim/ppc/cpu.c
+++ b/sim/ppc/cpu.c
@@ -68,8 +68,8 @@ struct _cpu {
memory_reservation reservation;
/* offset from event time to this cpu's idea of the local time */
- signed64 time_base_local_time;
- signed64 decrementer_local_time;
+ int64_t time_base_local_time;
+ int64_t decrementer_local_time;
event_entry_tag decrementer_event;
};
@@ -229,7 +229,7 @@ cpu_error(cpu *processor,
/* The processors local concept of time */
INLINE_CPU\
-(signed64)
+(int64_t)
cpu_get_time_base(cpu *processor)
{
return (event_queue_time(processor->events)
@@ -239,14 +239,14 @@ cpu_get_time_base(cpu *processor)
INLINE_CPU\
(void)
cpu_set_time_base(cpu *processor,
- signed64 time_base)
+ int64_t time_base)
{
processor->time_base_local_time = (event_queue_time(processor->events)
- time_base);
}
INLINE_CPU\
-(signed32)
+(int32_t)
cpu_get_decrementer(cpu *processor)
{
return (processor->decrementer_local_time
@@ -265,9 +265,9 @@ cpu_decrement_event(void *data)
INLINE_CPU\
(void)
cpu_set_decrementer(cpu *processor,
- signed32 decrementer)
+ int32_t decrementer)
{
- signed64 old_decrementer = cpu_get_decrementer(processor);
+ int64_t old_decrementer = cpu_get_decrementer(processor);
event_queue_deschedule(processor->events, processor->decrementer_event);
processor->decrementer_event = NULL;
processor->decrementer_local_time = (event_queue_time(processor->events)
diff --git a/sim/ppc/cpu.h b/sim/ppc/cpu.h
index 7dc6074b9c6..c7a08711271 100644
--- a/sim/ppc/cpu.h
+++ b/sim/ppc/cpu.h
@@ -120,22 +120,22 @@ EXTERN_CPU\
/* The processors local concept of time */
INLINE_CPU\
-(signed64) cpu_get_time_base
+(int64_t) cpu_get_time_base
(cpu *processor);
INLINE_CPU\
(void) cpu_set_time_base
(cpu *processor,
- signed64 time_base);
+ int64_t time_base);
INLINE_CPU\
-(signed32) cpu_get_decrementer
+(int32_t) cpu_get_decrementer
(cpu *processor);
INLINE_CPU\
(void) cpu_set_decrementer
(cpu *processor,
- signed32 decrementer);
+ int32_t decrementer);
#if WITH_IDECODE_CACHE_SIZE
diff --git a/sim/ppc/device.c b/sim/ppc/device.c
index 47fa7518f7e..4537e89b38d 100644
--- a/sim/ppc/device.c
+++ b/sim/ppc/device.c
@@ -989,7 +989,7 @@ device_add_boolean_property(device *me,
const char *property,
int boolean)
{
- signed32 new_boolean = (boolean ? -1 : 0);
+ int32_t new_boolean = (boolean ? -1 : 0);
device_add_property(me, property, boolean_property,
&new_boolean, sizeof(new_boolean),
&new_boolean, sizeof(new_boolean),
@@ -1879,7 +1879,7 @@ device_instance_to_external(device_instance *instance)
INLINE_DEVICE\
(event_entry_tag)
device_event_queue_schedule(device *me,
- signed64 delta_time,
+ int64_t delta_time,
device_event_handler *handler,
void *data)
{
@@ -1899,7 +1899,7 @@ device_event_queue_deschedule(device *me,
}
INLINE_DEVICE\
-(signed64)
+(int64_t)
device_event_queue_time(device *me)
{
return event_queue_time(psim_event_queue(me->system));
diff --git a/sim/ppc/device.h b/sim/ppc/device.h
index 68a2d24dd8d..bd539095160 100644
--- a/sim/ppc/device.h
+++ b/sim/ppc/device.h
@@ -780,7 +780,7 @@ typedef void device_event_handler(void *data);
INLINE_DEVICE\
(event_entry_tag) device_event_queue_schedule
(device *me,
- signed64 delta_time,
+ int64_t delta_time,
device_event_handler *handler,
void *data);
@@ -790,7 +790,7 @@ INLINE_DEVICE\
event_entry_tag event_to_remove);
INLINE_DEVICE\
-(signed64) device_event_queue_time
+(int64_t) device_event_queue_time
(device *me);
#endif /* _DEVICE_H_ */
diff --git a/sim/ppc/double.c b/sim/ppc/double.c
index 615797fc45e..d52c4d27fc0 100644
--- a/sim/ppc/double.c
+++ b/sim/ppc/double.c
@@ -24,16 +24,16 @@
#include "basics.h"
#include "ansidecls.h"
-#define SFtype unsigned32
-#define DFtype unsigned64
+#define SFtype uint32_t
+#define DFtype uint64_t
-#define HItype signed16
-#define SItype signed32
-#define DItype signed64
+#define HItype int16_t
+#define SItype int32_t
+#define DItype int64_t
-#define UHItype unsigned16
-#define USItype unsigned32
-#define UDItype unsigned64
+#define UHItype uint16_t
+#define USItype uint32_t
+#define UDItype uint64_t
#define US_SOFTWARE_GOFAST
diff --git a/sim/ppc/e500.igen b/sim/ppc/e500.igen
index 5b9c5538ab5..dce18655a8e 100644
--- a/sim/ppc/e500.igen
+++ b/sim/ppc/e500.igen
@@ -37,8 +37,8 @@
} while (0)
# Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register
-void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned nSPR
- const unsigned32 int_mask = out_mask | in_mask;
+void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const unsigned nSPR
+ const uint32_t int_mask = out_mask | in_mask;
model_busy *busy_ptr;
while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) {
@@ -60,23 +60,23 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
# SPE Modulo Fractional Multiplication handling support
#
-:function:e500::unsigned64:ev_multiply16_smf:signed16 a, signed16 b, int *sat
- signed32 a32 = a, b32 = b, rv32;
+:function:e500::uint64_t:ev_multiply16_smf:int16_t a, int16_t b, int *sat
+ int32_t a32 = a, b32 = b, rv32;
rv32 = a * b;
*sat = (rv32 & (3<<30)) == (3<<30);
- return (signed64)rv32 << 1;
+ return (int64_t)rv32 << 1;
-:function:e500::unsigned64:ev_multiply32_smf:signed32 a, signed32 b, int *sat
- signed64 rv64, a64 = a, b64 = b;
+:function:e500::uint64_t:ev_multiply32_smf:int32_t a, int32_t b, int *sat
+ int64_t rv64, a64 = a, b64 = b;
rv64 = a64 * b64;
- *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62);
+ *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62);
/* Loses top sign bit. */
return rv64 << 1;
#
# SPE Saturation handling support
#
-:function:e500::signed32:ev_multiply16_ssf:signed16 a, signed16 b, int *sat
- signed32 rv32;
+:function:e500::int32_t:ev_multiply16_ssf:int16_t a, int16_t b, int *sat
+ int32_t rv32;
if (a == 0xffff8000 && b == 0xffff8000)
{
rv32 = 0x7fffffffL;
@@ -85,15 +85,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
}
else
{
- signed32 a32 = a, b32 = b;
+ int32_t a32 = a, b32 = b;
rv32 = a * b;
* sat = (rv32 & (3<<30)) == (3<<30);
- return (signed64)rv32 << 1;
+ return (int64_t)rv32 << 1;
}
-:function:e500::signed64:ev_multiply32_ssf:signed32 a, signed32 b, int *sat
- signed64 rv64;
+:function:e500::int64_t:ev_multiply32_ssf:int32_t a, int32_t b, int *sat
+ int64_t rv64;
if (a == 0x80000000 && b == 0x80000000)
{
rv64 = 0x7fffffffffffffffLL;
@@ -102,9 +102,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
}
else
{
- signed64 a64 = a, b64 = b;
+ int64_t a64 = a, b64 = b;
rv64 = a64 * b64;
- *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62);
+ *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62);
/* Loses top sign bit. */
return rv64 << 1;
}
@@ -114,21 +114,21 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
:function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor
- unsigned64 guard;
+ uint64_t guard;
guard = sim_fpu_guard(a, 0);
if (guard & 1)
EV_SET_SPEFSCR_BITS(fg);
if (guard & ~1)
EV_SET_SPEFSCR_BITS(fx);
-:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, unsigned32 packed
+:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, uint32_t packed
sim_fpu_32to (dst, packed);
/* Set normally unused fields to allow booke arithmetic. */
if (dst->class == sim_fpu_class_infinity)
{
dst->normal_exp = 128;
- dst->fraction = ((unsigned64)1 << 60);
+ dst->fraction = ((uint64_t)1 << 60);
}
else if (dst->class == sim_fpu_class_qnan
|| dst->class == sim_fpu_class_snan)
@@ -136,7 +136,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
dst->normal_exp = 128;
/* This is set, but without the implicit bit, so we have to or
in the implicit bit. */
- dst->fraction |= ((unsigned64)1 << 60);
+ dst->fraction |= ((uint64_t)1 << 60);
}
:function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor
@@ -207,9 +207,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
return invalid_operand || overflow_result || underflow_result;
-:function:e500::unsigned32:ev_fs_add:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_add:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int exception;
booke_sim_fpu_32to (&a, aa);
@@ -223,9 +223,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
ev_check_guard(&d, fg, fx, processor);
return w;
-:function:e500::unsigned32:ev_fs_sub:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_sub:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int exception;
booke_sim_fpu_32to (&a, aa);
@@ -244,7 +244,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
# sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN.
# The booke algorithms require exp values, so we fake them here.
# fixme: It also apparently does the same for zero, but should not.
-:function:e500::unsigned32:booke_sim_fpu_exp:sim_fpu *x
+:function:e500::uint32_t:booke_sim_fpu_exp:sim_fpu *x
int y = sim_fpu_is (x);
if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO)
return 0;
@@ -254,9 +254,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
else
return sim_fpu_exp (x);
-:function:e500::unsigned32:ev_fs_mul:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_mul:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int sa, sb, ea, eb, ei;
sim_fpu_32to (&a, aa);
sim_fpu_32to (&b, bb);
@@ -296,9 +296,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
}
return w;
-:function:e500::unsigned32:ev_fs_div:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_div:uint32_t aa, uint32_t bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int sa, sb, ea, eb, ei;
sim_fpu_32to (&a, aa);
@@ -381,7 +381,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh + *rAh;
w2 = *rB + *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -389,7 +389,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh + IMM;
w2 = *rB + IMM;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -397,7 +397,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh - *rAh;
w2 = *rB - *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -405,7 +405,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh - IMM;
w2 = *rB - IMM;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -413,7 +413,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value
- signed32 w1, w2;
+ int32_t w1, w2;
w1 = *rAh;
if (w1 < 0 && w1 != 0x80000000)
w1 = -w1;
@@ -424,7 +424,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate
- signed32 w1, w2;
+ int32_t w1, w2;
w1 = *rAh;
/* the negative most negative number is the most negative number */
if (w1 != 0x80000000)
@@ -436,7 +436,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte
- unsigned64 w1, w2;
+ uint64_t w1, w2;
w1 = *rAh & 0xff;
if (w1 & 0x80)
w1 |= 0xffffff00;
@@ -447,7 +447,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0);
0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word
- unsigned64 w1, w2;
+ uint64_t w1, w2;
w1 = *rAh & 0xffff;
if (w1 & 0x8000)
w1 |= 0xffff0000;
@@ -458,49 +458,49 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh & *rAh;
w2 = *rB & *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh | *rAh;
w2 = *rB | *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh ^ *rAh;
w2 = *rB ^ *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ~(*rBh & *rAh);
w2 = ~(*rB & *rA);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ~(*rBh | *rAh);
w2 = ~(*rB | *rA);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = (~*rBh) ^ *rAh;
w2 = (~*rB) ^ *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = (~*rBh) & *rAh;
w2 = (~*rB) & *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -508,7 +508,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = (~*rBh) | *rAh;
w2 = (~*rB) | *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -516,76 +516,76 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word
- unsigned32 nh, nl, w1, w2;
+ uint32_t nh, nl, w1, w2;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((unsigned32)*rAh) << nh | ((unsigned32)*rAh) >> (32 - nh);
- w2 = ((unsigned32)*rA) << nl | ((unsigned32)*rA) >> (32 - nl);
+ w1 = ((uint32_t)*rAh) << nh | ((uint32_t)*rAh) >> (32 - nh);
+ w2 = ((uint32_t)*rA) << nl | ((uint32_t)*rA) >> (32 - nl);
EV_SET_REG2(*rSh, *rS, w1, w2);
//printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate
- unsigned32 w1, w2, imm;
- imm = (unsigned32)UIMM;
- w1 = ((unsigned32)*rAh) << imm | ((unsigned32)*rAh) >> (32 - imm);
- w2 = ((unsigned32)*rA) << imm | ((unsigned32)*rA) >> (32 - imm);
+ uint32_t w1, w2, imm;
+ imm = (uint32_t)UIMM;
+ w1 = ((uint32_t)*rAh) << imm | ((uint32_t)*rAh) >> (32 - imm);
+ w2 = ((uint32_t)*rA) << imm | ((uint32_t)*rA) >> (32 - imm);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word
- unsigned32 nh, nl, w1, w2;
+ uint32_t nh, nl, w1, w2;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((unsigned32)*rAh) << nh;
- w2 = ((unsigned32)*rA) << nl;
+ w1 = ((uint32_t)*rAh) << nh;
+ w2 = ((uint32_t)*rA) << nl;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate
- unsigned32 w1, w2, imm = UIMM;
- w1 = ((unsigned32)*rAh) << imm;
- w2 = ((unsigned32)*rA) << imm;
+ uint32_t w1, w2, imm = UIMM;
+ w1 = ((uint32_t)*rAh) << imm;
+ w2 = ((uint32_t)*rA) << imm;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed
- signed32 w1, w2;
- unsigned32 nh, nl;
+ int32_t w1, w2;
+ uint32_t nh, nl;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((signed32)*rAh) >> nh;
- w2 = ((signed32)*rA) >> nl;
+ w1 = ((int32_t)*rAh) >> nh;
+ w2 = ((int32_t)*rA) >> nl;
EV_SET_REG2(*rSh, *rS, w1, w2);
//printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned
- unsigned32 w1, w2, nh, nl;
+ uint32_t w1, w2, nh, nl;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((unsigned32)*rAh) >> nh;
- w2 = ((unsigned32)*rA) >> nl;
+ w1 = ((uint32_t)*rAh) >> nh;
+ w2 = ((uint32_t)*rA) >> nl;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed
- signed32 w1, w2;
- unsigned32 imm = UIMM;
- w1 = ((signed32)*rAh) >> imm;
- w2 = ((signed32)*rA) >> imm;
+ int32_t w1, w2;
+ uint32_t imm = UIMM;
+ w1 = ((int32_t)*rAh) >> imm;
+ w2 = ((int32_t)*rA) >> imm;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned
- unsigned32 w1, w2, imm = UIMM;
- w1 = ((unsigned32)*rAh) >> imm;
- w2 = ((unsigned32)*rA) >> imm;
+ uint32_t w1, w2, imm = UIMM;
+ w1 = ((uint32_t)*rAh) >> imm;
+ w2 = ((uint32_t)*rA) >> imm;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word
- unsigned32 w1, w2, mask, c1, c2;
+ uint32_t w1, w2, mask, c1, c2;
for (c1 = 0, mask = 0x80000000, w1 = *rAh;
!(w1 & mask) && mask != 0; mask >>= 1)
c1++;
@@ -596,7 +596,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word
- unsigned32 w1, w2, mask, sign_bit, c1, c2;
+ uint32_t w1, w2, mask, sign_bit, c1, c2;
for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask;
((w1 & mask) == sign_bit) && mask != 0;
mask >>= 1, sign_bit >>= 1)
@@ -609,43 +609,43 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word
- unsigned32 w1, w2;
- w1 = ((unsigned32)*rAh + 0x8000) & 0xffff0000;
- w2 = ((unsigned32)*rA + 0x8000) & 0xffff0000;
+ uint32_t w1, w2;
+ w1 = ((uint32_t)*rAh + 0x8000) & 0xffff0000;
+ w2 = ((uint32_t)*rA + 0x8000) & 0xffff0000;
EV_SET_REG2(*rSh, *rS, w1, w2);
//printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh;
w2 = *rBh;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rA;
w2 = *rB;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rA;
w2 = *rBh;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh;
w2 = *rB;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate
- unsigned32 w;
+ uint32_t w;
w = SIMM & 0x1f;
if (w & 0x10)
w |= 0xffffffe0;
@@ -653,13 +653,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, 0, 0);
0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate
- unsigned32 w;
+ uint32_t w;
w = SIMM << 27;
EV_SET_REG2(*rSh, *rS, w, w);
PPC_INSN_INT(RS_BITMASK, 0, 0);
0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed
- signed32 ah, al, bh, bl;
+ int32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -678,7 +678,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned
- unsigned32 ah, al, bh, bl;
+ uint32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -697,7 +697,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed
- signed32 ah, al, bh, bl;
+ int32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -716,7 +716,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned
- unsigned32 ah, al, bh, bl;
+ uint32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -735,7 +735,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal
- unsigned32 ah, al, bh, bl;
+ uint32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -755,7 +755,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select
- unsigned32 w1, w2;
+ uint32_t w1, w2;
int cr;
cr = CR_FIELD(CRFS);
if (cr & 8)
@@ -770,7 +770,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment
- unsigned32 w1, w2, a, d, mask;
+ uint32_t w1, w2, a, d, mask;
mask = (*rB) & 0xffff;
a = (*rA) & 0xffff;
d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask));
@@ -783,14 +783,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -799,14 +799,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -815,39 +815,39 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int dummy;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_smf (al, bl, & dummy);
th = ev_multiply16_smf (ah, bh, & dummy);
EV_SET_REG2 (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate
- signed32 al, ah, bl, bh;
- signed32 tl, th;
+ int32_t al, ah, bl, bh;
+ int32_t tl, th;
int dummy;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_smf (al, bl, & dummy);
th = ev_multiply16_smf (ah, bh, & dummy);
EV_SET_REG2_ACC (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer
- signed32 al, ah, bl, bh, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2(*rSh, *rS, th, tl);
@@ -855,11 +855,11 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate
- signed32 al, ah, bl, bh, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
@@ -867,36 +867,36 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -905,14 +905,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -921,14 +921,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional
- signed16 al, ah, bl, bh;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int64_t tl, th;
int movl, movh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_smf (al, bl, &movl);
th = ev_multiply16_smf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, th, tl);
@@ -936,75 +936,75 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int dummy;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_smf (al, bl, & dummy);
th = ev_multiply16_smf (ah, bh, & dummy);
EV_SET_REG2_ACC (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2 (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate
- signed32 al, ah, bl, bh, tl, th;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ int32_t al, ah, bl, bh, tl, th;
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2;
+ int64_t tl, th;
int movl, movh, ovl, ovh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
t1 = ev_multiply16_ssf (ah, bh, &movh);
t2 = ev_multiply16_ssf (al, bl, &movl);
th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1);
@@ -1017,13 +1017,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1038,26 +1038,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
- t1 = ((signed64)ah * bh) << 1;
- t2 = ((signed64)al * bl) << 1;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
+ t1 = ((int64_t)ah * bh) << 1;
+ t2 = ((int64_t)al * bl) << 1;
th = EV_ACCHIGH + (t1 & 0xffffffff);
tl = EV_ACCLOW + (t2 & 0xffffffff);
EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1068,18 +1068,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
- signed64 tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
+ int64_t tl, th;
int ovl, ovh;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
- th = (signed64)EV_ACCHIGH + (signed64)t1;
- tl = (signed64)EV_ACCLOW + (signed64)t2;
+ th = (int64_t)EV_ACCHIGH + (int64_t)t1;
+ tl = (int64_t)EV_ACCLOW + (int64_t)t2;
ovh = EV_SAT_P_U32(th);
ovl = EV_SAT_P_U32(tl);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
@@ -1090,13 +1090,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words
- unsigned32 al, ah, bl, bh;
- unsigned32 t1, t2;
- signed64 tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh;
+ uint32_t t1, t2;
+ int64_t tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1107,15 +1107,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2;
+ int64_t tl, th;
int movl, movh, ovl, ovh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
t1 = ev_multiply16_ssf (ah, bh, &movh);
t2 = ev_multiply16_ssf (al, bl, &movl);
th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1);
@@ -1128,13 +1128,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1149,14 +1149,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2, th, tl;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2, th, tl;
int dummy;
- al = (signed16)EV_HIHALF(*rA);
- ah = (signed16)EV_HIHALF(*rAh);
- bl = (signed16)EV_HIHALF(*rB);
- bh = (signed16)EV_HIHALF(*rBh);
+ al = (int16_t)EV_HIHALF(*rA);
+ ah = (int16_t)EV_HIHALF(*rAh);
+ bl = (int16_t)EV_HIHALF(*rB);
+ bh = (int16_t)EV_HIHALF(*rBh);
t1 = ev_multiply16_smf (ah, bh, &dummy);
[...]
[diff truncated at 100000 bytes]
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2022-01-06 6:22 [binutils-gdb] sim: ppc: migrate to standard uintXX_t types Michael Frysinger
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