From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1879) id D28183858C2C; Thu, 24 Mar 2022 14:35:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D28183858C2C Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Simon Marchi To: gdb-cvs@sourceware.org Subject: =?utf-8?b?W2JpbnV0aWxzLWdkYl0gc2ltOiBmaXgg4oCcYWxsaWduZWTigJ0gdHlwb3M=?= X-Act-Checkin: binutils-gdb X-Git-Author: Reuben Thomas X-Git-Refname: refs/heads/master X-Git-Oldrev: f1a45585865a724d83133a2299768b5953d2ed94 X-Git-Newrev: c41524681bf2dad22390fe2b1cfbdeac1576e1e5 Message-Id: <20220324143545.D28183858C2C@sourceware.org> Date: Thu, 24 Mar 2022 14:35:45 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Mar 2022 14:35:45 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dc41524681bf2= dad22390fe2b1cfbdeac1576e1e5 commit c41524681bf2dad22390fe2b1cfbdeac1576e1e5 Author: Reuben Thomas Date: Thu Mar 24 12:05:21 2022 +0000 sim: fix =E2=80=9Calligned=E2=80=9D typos =20 Change-Id: Ifd574e38524dd4f1cf0fc003e0c5c7499abc84a0 Diff: --- sim/common/sim-core.h | 4 ++-- sim/ppc/hw_init.c | 2 +- sim/ppc/std-config.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h index 5f152ee0552..df4e3e17a7b 100644 --- a/sim/common/sim-core.h +++ b/sim/common/sim-core.h @@ -248,7 +248,7 @@ extern void *sim_core_trans_addr order (including xor endian). Should the transfer fail, the operation shall abort (no return). =20 - ALIGNED assumes yhat the specified ADDRESS is correctly alligned + ALIGNED assumes that the specified ADDRESS is correctly aligned for an N byte transfer (no alignment checks are made). Passing an incorrectly aligned ADDRESS is erroneous. =20 @@ -256,7 +256,7 @@ extern void *sim_core_trans_addr of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being taken should the check fail. =20 - MISSALIGNED transfers the data regardless. + MISALIGNED transfers the data regardless. =20 Misaligned xor-endian accesses are broken into a sequence of transfers each <=3D WITH_XOR_ENDIAN bytes */ diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c index 3d58833bb3d..66f205851d5 100644 --- a/sim/ppc/hw_init.c +++ b/sim/ppc/hw_init.c @@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me, const unsigned sizeof_argv =3D sizeof_arguments(argv); const unsigned_word start_argv =3D start_envp - sizeof_argv; =20 - /* link register save address - alligned to a 16byte boundary */ + /* link register save address - aligned to a 16byte boundary */ const unsigned_word top_of_stack =3D ((start_argv - 2 * sizeof(unsigned_word)) & ~0xf); diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h index 0619d1dff19..e02d5946a73 100644 --- a/sim/ppc/std-config.h +++ b/sim/ppc/std-config.h @@ -183,7 +183,7 @@ extern int current_environment; This model. Instead allows both little and big endian modes to either take exceptions or handle miss aligned transfers. =20 - If 0 is specified then for big-endian mode miss alligned accesses + If 0 is specified then for big-endian mode miss aligned accesses are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the processor will fault on them (STRICT_ALIGNMENT). */