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From: Jeff Law <law@sourceware.org>
To: gdb-cvs@sourceware.org
Subject: [binutils-gdb] Fix for MUL instruction on the v850
Date: Wed, 30 Mar 2022 00:08:41 +0000 (GMT)	[thread overview]
Message-ID: <20220330000841.E656E3858C50@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5321c31bc78379a33f07dc7bef9256d05b942ad7

commit 5321c31bc78379a33f07dc7bef9256d05b942ad7
Author: Jeff Law <jeffreyalaw@gmail.com>
Date:   Tue Mar 29 20:05:51 2022 -0400

    Fix for MUL instruction on the v850
    
            * sim/v850/simops.c (Multiply64): Properly test if we need to
            negate either of the operands.
    
            * sim/testsuite/v850/mul.cgs: New test.

Diff:
---
 sim/testsuite/v850/mul.cgs | 15 +++++++++++++++
 sim/v850/simops.c          |  4 ++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/sim/testsuite/v850/mul.cgs b/sim/testsuite/v850/mul.cgs
new file mode 100644
index 00000000000..7d19b70c70b
--- /dev/null
+++ b/sim/testsuite/v850/mul.cgs
@@ -0,0 +1,15 @@
+# v850e mul
+# mach: v850e
+# as(v850e): -mv850e
+
+	.include "testutils.inc"
+
+# Trivial regression test for incorrect sign bit handling in mul
+
+	seti	-10, r1
+	seti 	2, r2
+	mul	r1, r2, r3
+	reg	r2, -20
+	reg	r3, -1
+
+	pass
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 8fac8bd9891..d2640577fc8 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -339,10 +339,10 @@ Multiply64 (int sign, unsigned long op0)
 	  
       sign = (op0 ^ op1) & 0x80000000;
 	  
-      if (((signed long) op0) < 0)
+      if (op0 & 0x80000000)
 	op0 = - op0;
 	  
-      if (((signed long) op1) < 0)
+      if (op1 & 0x80000000)
 	op1 = - op1;
     }


                 reply	other threads:[~2022-03-30  0:08 UTC|newest]

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