From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1983) id 313113858C83; Tue, 26 Apr 2022 15:02:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 313113858C83 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Carl Love To: gdb-cvs@sourceware.org Subject: [binutils-gdb] PowerPC: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.e X-Act-Checkin: binutils-gdb X-Git-Author: Carl Love X-Git-Refname: refs/heads/master X-Git-Oldrev: 3f0423f9130cdc3a6aecbb44435ad690b3aa9e99 X-Git-Newrev: 0b60b9634430caebb640ef9b943049bdc6aa8f6f Message-Id: <20220426150256.313113858C83@sourceware.org> Date: Tue, 26 Apr 2022 15:02:56 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Apr 2022 15:02:56 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D0b60b9634430= caebb640ef9b943049bdc6aa8f6f commit 0b60b9634430caebb640ef9b943049bdc6aa8f6f Author: Carl Love Date: Tue Apr 26 15:00:19 2022 +0000 PowerPC: Update expected floating point output for gdb.arch/altivec-reg= s.exp and gdb.arch/vsx-regs.exp =20 The format for printing the floating point values was changed by commit: =20 commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e Author: Tom Tromey Date: Thu Feb 17 13:43:59 2022 -0700 =20 Change how "print/x" displays floating-point value =20 Currently, "print/x" will display a floating-point value by first casting it to an integer type. This yields weird results like: =20 (gdb) print/x 1.5 $1 =3D 0x1 ... Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=3D16242 =20 The above change results in 417 regression test failures since the expe= cted Power vector register output no longer match. =20 This patch updates the expected Altivec floating point register prints = to the hexadecimal format for both big endian and little endian systems. = The patch also fixes a formatting isue with the decimal_vector expected val= ue assign statements. =20 The expected VSX vector_register1, vector_register1_vr, vector_register= 2, vector_register2_vr variables are updated to include the new float128 e= ntry. Additionally, the comment in the vsx expect file about the initializati= on of the vs registers is updated. =20 The patch has been tested on Power 10, Power 8 LE and Power 8 BE. Diff: --- gdb/testsuite/gdb.arch/altivec-regs.exp | 8 ++++---- gdb/testsuite/gdb.arch/vsx-regs.exp | 31 ++++++++++++++++-------------= -- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp b/gdb/testsuite/gdb.ar= ch/altivec-regs.exp index 7bae979b984..d4c13afa8a1 100644 --- a/gdb/testsuite/gdb.arch/altivec-regs.exp +++ b/gdb/testsuite/gdb.arch/altivec-regs.exp @@ -84,9 +84,9 @@ set endianness [get_endianness] # b) the register read (below) also works. =20 if {$endianness =3D=3D "big"} { -set vector_register ".uint128 =3D 0x1000000010000000100000001, v4_float = =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16 =3D .= 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 =3D .0x0, 0x0, 0x0, 0x1, = 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." +set vector_register ".uint128 =3D 0x1000000010000000100000001, v4_float = =3D .0x1, 0x1, 0x1, 0x1., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16 =3D .= 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 =3D .0x0, 0x0, 0x0, 0x1, = 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." } else { -set vector_register ".uint128 =3D 0x1000000010000000100000001, v4_float = =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16 =3D .= 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 =3D .0x1, 0x0, 0x0, 0x0, = 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." +set vector_register ".uint128 =3D 0x1000000010000000100000001, v4_float = =3D .0x1, 0x1, 0x1, 0x1., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16 =3D .= 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 =3D .0x1, 0x0, 0x0, 0x0, = 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." } =20 for {set i 0} {$i < 32} {incr i 1} { @@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1" "info reg= vscr" # the way gdb works. =20 if {$endianness =3D=3D "big"} { - set decimal_vector ".uint128 =3D 79228162532711081671548469249, v4_fl= oat =3D .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 =3D .1, 1, 1, 1., v8= _int16 =3D .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 =3D .0, 0, 0, 1, 0, 0, 0, 1, = 0, 0, 0, 1, 0, 0, 0, 1.." + set decimal_vector ".uint128 =3D 79228162532711081671548469249, v4_flo= at =3D .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 =3D .1, 1, 1, 1., v8_= int16 =3D .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 =3D .0, 0, 0, 1, 0, 0, 0, 1, 0= , 0, 0, 1, 0, 0, 0, 1.." } else { - set decimal_vector ".uint128 =3D 79228162532711081671548469249, v4_fl= oat =3D .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 =3D .1, 1, 1, 1., v8= _int16 =3D .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 =3D .1, 0, 0, 0, 1, 0, 0, 0, = 1, 0, 0, 0, 1, 0, 0, 0.." + set decimal_vector ".uint128 =3D 79228162532711081671548469249, v4_flo= at =3D .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 =3D .1, 1, 1, 1., v8_= int16 =3D .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 =3D .1, 0, 0, 0, 1, 0, 0, 0, 1= , 0, 0, 0, 1, 0, 0, 0.." } =20 for {set i 0} {$i < 32} {incr i 1} { diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/v= sx-regs.exp index 8b3841362fe..56fea796a9b 100644 --- a/gdb/testsuite/gdb.arch/vsx-regs.exp +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp @@ -61,29 +61,29 @@ set endianness [get_endianness] # Data sets used throughout the test =20 if {$endianness =3D=3D "big"} { - set vector_register1 ".uint128 =3D 0x3ff4cccccccccccd0000000000000000,= v2_double =3D .0x1, 0x0., v4_float =3D .0x1, 0xf9999998, 0x0, 0x0., v4_int= 32 =3D .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 =3D .0x3ff4, 0xcccc, 0x= cccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 =3D .0x3f, 0xf4, 0xcc, 0xcc, 0x= cc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." + set vector_register1 ".float128 =3D 0x3ff4cccccccccccd0000000000000000= , uint128 =3D 0x3ff4cccccccccccd0000000000000000, v2_double =3D .0x3ff4cccc= cccccccd, 0x0., v4_float =3D .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 = =3D .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 =3D .0x3ff4, 0xcccc, 0xccc= c, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 =3D .0x3f, 0xf4, 0xcc, 0xcc, 0xcc,= 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." =20 - set vector_register1_vr ".uint128 =3D 0x3ff4cccccccccccd00000001000000= 01, v4_float =3D .0x1, 0xf9999998, 0x0, 0x0., v4_int32 =3D .0x3ff4cccc, 0xc= ccccccd, 0x1, 0x1., v8_int16 =3D .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1,= 0x0, 0x1., v16_int8 =3D .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0= x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." + set vector_register1_vr ".uint128 =3D 0x3ff4cccccccccccd00000001000000= 01, v4_float =3D .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v4_int32 =3D .0x3ff4cc= cc, 0xcccccccd, 0x1, 0x1., v8_int16 =3D .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x= 0, 0x1, 0x0, 0x1., v16_int8 =3D .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, = 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." =20 - set vector_register2 "uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbeef, = v2_double =3D .0x8000000000000000, 0x8000000000000000., v4_float =3D .0x0, = 0x0, 0x0, 0x0., v4_int32 =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbee= f., v8_int16 =3D .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0= xbeef., v16_int8 =3D .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde,= 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." + set vector_register2 ".float128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbeef= , uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double =3D .0xdeadbeef= deadbeef, 0xdeadbeefdeadbeef., v4_float =3D .0xdeadbeef, 0xdeadbeef, 0xdead= beef, 0xdeadbeef., v4_int32 =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdead= beef., v8_int16 =3D .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead= , 0xbeef., v16_int8 =3D .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0x= de, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." =20 - set vector_register2_vr "uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbee= f, v4_float =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0xdeadbeef, 0xdeadbeef,= 0xdeadbeef, 0xdeadbeef., v8_int16 =3D .0xdead, 0xbeef, 0xdead, 0xbeef, 0xd= ead, 0xbeef, 0xdead, 0xbeef., v16_int8 =3D .0xde, 0xad, 0xbe, 0xef, 0xde, 0= xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." + set vector_register2_vr ".uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbe= ef, v4_float =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32= =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 =3D .0xdead= , 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 =3D .0x= de, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde,= 0xad, 0xbe, 0xef.." =20 - set vector_register3 ".uint128 =3D 0x1000000010000000100000001, v2_dou= ble =3D .0x0, 0x0., v4_float =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0x1, 0= x1, 0x1, 0x1., v8_int16 =3D .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_i= nt8 =3D .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0= x0, 0x0, 0x1.." + set vector_register3 ".float128 =3D 0x1000000010000000100000001, uint1= 28 =3D 0x1000000010000000100000001, v2_double =3D .0x100000001, 0x100000001= ., v4_float =3D .0x1, 0x1, 0x1, 0x1., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8= _int16 =3D .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 =3D .0x0, 0x0= , 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." =20 - set vector_register3_vr ".uint128 =3D 0x1000000010000000100000001, v4_= float =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16= =3D .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 =3D .0x0, 0x0, 0x0,= 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." + set vector_register3_vr ".uint128 =3D 0x1000000010000000100000001, v4_= float =3D .0x1, 0x1, 0x1, 0x1., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16= =3D .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 =3D .0x0, 0x0, 0x0,= 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." } else { - set vector_register1 ".uint128 =3D 0x3ff4cccccccccccd0000000000000000,= v2_double =3D .0x0, 0x1., v4_float =3D .0x0, 0x0, 0xf9999998, 0x1., v4_int= 32 =3D .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 =3D .0x0, 0x0, 0x0, 0x0= , 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 =3D .0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." + set vector_register1 ".float128 =3D 0x3ff4cccccccccccd0000000000000000= , uint128 =3D 0x3ff4cccccccccccd0000000000000000, v2_double =3D .0x0, 0x3ff= 4cccccccccccd., v4_float =3D .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v4_int32 = =3D .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 =3D .0x0, 0x0, 0x0, 0x0, 0= xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 =3D .0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." =20 - set vector_register1_vr ".uint128 =3D 0x3ff4cccccccccccd00000001000000= 01, v4_float =3D .0x0, 0x0, 0xf9999998, 0x1., v4_int32 =3D .0x1, 0x1, 0xccc= ccccd, 0x3ff4cccc., v8_int16 =3D .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xccc= c, 0x3ff4., v16_int8 =3D .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xc= c, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." + set vector_register1_vr ".uint128 =3D 0x3ff4cccccccccccd00000001000000= 01, v4_float =3D .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v4_int32 =3D .0x1, 0x1= , 0xcccccccd, 0x3ff4cccc., v8_int16 =3D .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc= , 0xcccc, 0x3ff4., v16_int8 =3D .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x= cd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." =20 - set vector_register2 "uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbeef, = v2_double =3D .0x8000000000000000, 0x8000000000000000., v4_float =3D .0x0, = 0x0, 0x0, 0x0., v4_int32 =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbee= f., v8_int16 =3D .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0= xdead., v16_int8 =3D .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef,= 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." + set vector_register2 ".float128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbeef= , uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double =3D .0xdeadbeef= deadbeef, 0xdeadbeefdeadbeef., v4_float =3D .0xdeadbeef, 0xdeadbeef, 0xdead= beef, 0xdeadbeef., v4_int32 =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdead= beef., v8_int16 =3D .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef= , 0xdead., v16_int8 =3D .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0x= ef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." =20 - set vector_register2_vr "uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbee= f, v4_float =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0xdeadbeef, 0xdeadbeef,= 0xdeadbeef, 0xdeadbeef., v8_int16 =3D .0xbeef, 0xdead, 0xbeef, 0xdead, 0xb= eef, 0xdead, 0xbeef, 0xdead., v16_int8 =3D .0xef, 0xbe, 0xad, 0xde, 0xef, 0= xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." + set vector_register2_vr ".uint128 =3D 0xdeadbeefdeadbeefdeadbeefdeadbe= ef, v4_float =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32= =3D .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 =3D .0xbeef= , 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 =3D .0x= ef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef,= 0xbe, 0xad, 0xde.." =20 - set vector_register3 ".uint128 =3D 0x1000000010000000100000001, v2_dou= ble =3D .0x0, 0x0., v4_float =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0x1, 0= x1, 0x1, 0x1., v8_int16 =3D .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_i= nt8 =3D .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0= x0, 0x0, 0x0.." + set vector_register3 ".float128 =3D 0x1000000010000000100000001, uint1= 28 =3D 0x1000000010000000100000001, v2_double =3D .0x100000001, 0x100000001= ., v4_float =3D .0x1, 0x1, 0x1, 0x1., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8= _int16 =3D .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 =3D .0x1, 0x0= , 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." =20 - set vector_register3_vr ".uint128 =3D 0x1000000010000000100000001, v4_= float =3D .0x0, 0x0, 0x0, 0x0., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16= =3D .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 =3D .0x1, 0x0, 0x0,= 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." + set vector_register3_vr ".uint128 =3D 0x1000000010000000100000001, v4_= float =3D .0x1, 0x1, 0x1, 0x1., v4_int32 =3D .0x1, 0x1, 0x1, 0x1., v8_int16= =3D .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 =3D .0x1, 0x0, 0x0,= 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." } =20 set float_register ".raw 0xdeadbeefdeadbeef." @@ -93,12 +93,13 @@ set float_register ".raw 0xdeadbeefdeadbeef." # after updates to F*. # Since dl_main uses some VS* registers, and per inspection their values a= re # no longer zero when our test reaches main(), we need to explicitly -# initialize the doubleword1 portions before we run our tests against -# values currently in those registers. +# initialize the VS* registers before we run our tests against the values +# currently in those registers. =20 -# 0: Initialize the (doubleword 1) portion of the VS0-VS31 registers. +# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31 registers. for {set i 0} {$i < 32} {incr i 1} { gdb_test_no_output "set \$vs$i.v2_double\[0\] =3D 0" + gdb_test_no_output "set \$vs$i.v2_double\[1\] =3D 0" } =20 # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.