From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 35E183857C4D; Wed, 27 Apr 2022 14:51:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 35E183857C4D Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Christophe Lyon To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/arm: Introduce arm_cache_init X-Act-Checkin: binutils-gdb X-Git-Author: Christophe Lyon X-Git-Refname: refs/heads/master X-Git-Oldrev: 9074667a8583b33ff1b9590232c15e67f2d1d607 X-Git-Newrev: 0824193fd31467b6ff39132d0d72aaa9c01cc9aa Message-Id: <20220427145127.35E183857C4D@sourceware.org> Date: Wed, 27 Apr 2022 14:51:27 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Apr 2022 14:51:27 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D0824193fd314= 67b6ff39132d0d72aaa9c01cc9aa commit 0824193fd31467b6ff39132d0d72aaa9c01cc9aa Author: Christophe Lyon Date: Fri Apr 1 10:22:12 2022 +0100 gdb/arm: Introduce arm_cache_init =20 This patch is a preparation for the rest of the series and adds two arm_cache_init helper functions. It updates every place that updates cache->saved_regs to call the helper instead. =20 Signed-off-by: Torbj=C3=B6rn Svensson Signed-off-by: Christophe Lyon Signed-off-by: Christophe Lyon Diff: --- gdb/arm-tdep.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 6b4b00993fa..f393a3e4ad6 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -292,8 +292,29 @@ struct arm_prologue_cache =20 /* Saved register offsets. */ trad_frame_saved_reg *saved_regs; + + arm_prologue_cache() =3D default; }; =20 +/* Initialize CACHE fields for which zero is not adequate (CACHE is + expected to have been ZALLOC'ed before calling this function). */ + +static void +arm_cache_init (struct arm_prologue_cache *cache, struct gdbarch *gdbarch) +{ + cache->saved_regs =3D trad_frame_alloc_saved_regs (gdbarch); +} + +/* Similar to the previous function, but extracts GDBARCH from FRAME. */ + +static void +arm_cache_init (struct arm_prologue_cache *cache, struct frame_info *frame) +{ + struct gdbarch *gdbarch =3D get_frame_arch (frame); + + arm_cache_init (cache, gdbarch); +} + namespace { =20 /* Abstract class to read ARM instructions from memory. */ @@ -1981,7 +2002,7 @@ arm_make_prologue_cache (struct frame_info *this_fram= e) CORE_ADDR unwound_fp; =20 cache =3D FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs =3D trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); =20 arm_scan_prologue (this_frame, cache); =20 @@ -2454,7 +2475,7 @@ arm_exidx_fill_cache (struct frame_info *this_frame, = gdb_byte *entry) =20 struct arm_prologue_cache *cache; cache =3D FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs =3D trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); =20 for (;;) { @@ -2848,7 +2869,7 @@ arm_make_epilogue_frame_cache (struct frame_info *thi= s_frame) int reg; =20 cache =3D FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs =3D trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); =20 /* Still rely on the offset calculated from prologue. */ arm_scan_prologue (this_frame, cache); @@ -3009,7 +3030,7 @@ arm_make_stub_cache (struct frame_info *this_frame) struct arm_prologue_cache *cache; =20 cache =3D FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs =3D trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); =20 cache->prev_sp =3D get_frame_register_unsigned (this_frame, ARM_SP_REGNU= M); =20 @@ -3087,7 +3108,7 @@ arm_m_exception_cache (struct frame_info *this_frame) uint32_t secure_stack_used; =20 cache =3D FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs =3D trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); =20 /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" describes which bits in LR that define which stack was used prior @@ -13851,7 +13872,7 @@ arm_analyze_prologue_test () =20 test_arm_instruction_reader mem_reader (insns); arm_prologue_cache cache; - cache.saved_regs =3D trad_frame_alloc_saved_regs (gdbarch); + arm_cache_init (&cache, gdbarch); =20 arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_re= ader); }