From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1936) id 4FE513858C56; Tue, 3 May 2022 23:10:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4FE513858C56 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: John Baldwin To: gdb-cvs@sourceware.org Subject: [binutils-gdb] Read the tpidruro register from NT_ARM_TLS core dump notes on FreeBSD/arm. X-Act-Checkin: binutils-gdb X-Git-Author: John Baldwin X-Git-Refname: refs/heads/master X-Git-Oldrev: 92d48a1e4eac54db11f1a110328672394fce2853 X-Git-Newrev: 099fbce0accf209677e041fd9dc10bcb4a5eb578 Message-Id: <20220503231033.4FE513858C56@sourceware.org> Date: Tue, 3 May 2022 23:10:33 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 May 2022 23:10:33 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D099fbce0accf= 209677e041fd9dc10bcb4a5eb578 commit 099fbce0accf209677e041fd9dc10bcb4a5eb578 Author: John Baldwin Date: Tue May 3 16:05:10 2022 -0700 Read the tpidruro register from NT_ARM_TLS core dump notes on FreeBSD/a= rm. Diff: --- gdb/arm-fbsd-nat.c | 2 +- gdb/arm-fbsd-tdep.c | 32 ++++++++++++++++++++++++++------ gdb/arm-fbsd-tdep.h | 5 ++++- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/gdb/arm-fbsd-nat.c b/gdb/arm-fbsd-nat.c index 3106d73cc3a..c32924de735 100644 --- a/gdb/arm-fbsd-nat.c +++ b/gdb/arm-fbsd-nat.c @@ -72,7 +72,7 @@ arm_fbsd_nat_target::read_description () { const struct target_desc *desc; =20 - desc =3D arm_fbsd_read_description_auxv (this); + desc =3D arm_fbsd_read_description_auxv (this, false); if (desc =3D=3D NULL) desc =3D this->beneath ()->read_description (); return desc; diff --git a/gdb/arm-fbsd-tdep.c b/gdb/arm-fbsd-tdep.c index 06745a36186..a27dfb2fb4a 100644 --- a/gdb/arm-fbsd-tdep.c +++ b/gdb/arm-fbsd-tdep.c @@ -163,6 +163,24 @@ arm_fbsd_iterate_over_regset_sections (struct gdbarch = *gdbarch, cb (".reg", ARM_FBSD_SIZEOF_GREGSET, ARM_FBSD_SIZEOF_GREGSET, &arm_fbsd_gregset, NULL, cb_data); =20 + if (tdep->tls_regnum > 0) + { + const struct regcache_map_entry arm_fbsd_tlsregmap[] =3D + { + { 1, tdep->tls_regnum, 4 }, + { 0 } + }; + + const struct regset arm_fbsd_tlsregset =3D + { + arm_fbsd_tlsregmap, + regcache_supply_regset, regcache_collect_regset + }; + + cb (".reg-aarch-tls", ARM_FBSD_SIZEOF_TLSREGSET, ARM_FBSD_SIZEOF_TLS= REGSET, + &arm_fbsd_tlsregset, NULL, cb_data); + } + /* While FreeBSD/arm cores do contain a NT_FPREGSET / ".reg2" register set, it is not populated with register values by the kernel but just contains all zeroes. */ @@ -175,12 +193,12 @@ arm_fbsd_iterate_over_regset_sections (struct gdbarch= *gdbarch, vector. */ =20 const struct target_desc * -arm_fbsd_read_description_auxv (struct target_ops *target) +arm_fbsd_read_description_auxv (struct target_ops *target, bool tls) { CORE_ADDR arm_hwcap =3D 0; =20 if (target_auxv_search (target, AT_FREEBSD_HWCAP, &arm_hwcap) !=3D 1) - return nullptr; + return arm_read_description (ARM_FP_TYPE_NONE, tls); =20 if (arm_hwcap & HWCAP_VFP) { @@ -188,12 +206,12 @@ arm_fbsd_read_description_auxv (struct target_ops *ta= rget) return aarch32_read_description (); else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPD32)) =3D=3D (HWCAP_VFPv3 | HWCAP_VFPD32)) - return arm_read_description (ARM_FP_TYPE_VFPV3, false); + return arm_read_description (ARM_FP_TYPE_VFPV3, tls); else - return arm_read_description (ARM_FP_TYPE_VFPV2, false); + return arm_read_description (ARM_FP_TYPE_VFPV2, tls); } =20 - return nullptr; + return arm_read_description (ARM_FP_TYPE_NONE, tls); } =20 /* Implement the "core_read_description" gdbarch method. */ @@ -203,7 +221,9 @@ arm_fbsd_core_read_description (struct gdbarch *gdbarch, struct target_ops *target, bfd *abfd) { - return arm_fbsd_read_description_auxv (target); + asection *tls =3D bfd_get_section_by_name (abfd, ".reg-aarch-tls"); + + return arm_fbsd_read_description_auxv (target, tls !=3D nullptr); } =20 /* Implement the 'init_osabi' method of struct gdb_osabi_handler. */ diff --git a/gdb/arm-fbsd-tdep.h b/gdb/arm-fbsd-tdep.h index 633dafad75d..193eb76df3c 100644 --- a/gdb/arm-fbsd-tdep.h +++ b/gdb/arm-fbsd-tdep.h @@ -26,6 +26,9 @@ PC, and CPSR registers. */ #define ARM_FBSD_SIZEOF_GREGSET (17 * 4) =20 +/* The TLS regset consists of a single register. */ +#define ARM_FBSD_SIZEOF_TLSREGSET (4) + /* The VFP regset consists of 32 D registers plus FPSCR, and the whole structure is padded to 64-bit alignment. */ #define ARM_FBSD_SIZEOF_VFPREGSET (33 * 8) @@ -40,6 +43,6 @@ extern const struct regset arm_fbsd_vfpregset; #define HWCAP_VFPD32 0x00080000 =20 extern const struct target_desc * -arm_fbsd_read_description_auxv (struct target_ops *target); +arm_fbsd_read_description_auxv (struct target_ops *target, bool tls); =20 #endif /* ARM_FBSD_TDEP_H */